Soft-start switch circuit

Abstract

One example includes a switch circuit. The switch circuit includes a transistor configured to activate in response to an activation voltage at an activation terminal of the transistor. The switch circuit also includes a current source coupled to the activation terminal and being configured to generate an activation current. The switch circuit further includes a driver control circuit interconnecting the activation terminal and a voltage rail. The driver control circuit includes digital counter logic configured to cycle through a predetermined number of count values based on an oscillator signal. The driver control circuit is configured to adjust an amplitude of the activation voltage at each of the predetermined number of count values based on the activation current to provide a soft-start activation of the transistor.

What is claimed is: 
     
         1 . A switch circuit comprising:
 a transistor configured to activate in response to an activation voltage at an activation terminal of the transistor;   a current source coupled to the activation terminal and being configured to generate an activation current; and   a driver control circuit interconnecting the activation terminal and a voltage rail, the driver control circuit comprising digital counter logic configured to cycle through a predetermined number of count values based on an oscillator signal, the driver control circuit being configured to adjust an amplitude of the activation voltage at each of the predetermined number of count values based on the activation current to provide a soft-start activation of the transistor.   
     
     
         2 . The circuit of  claim 1 , wherein the driver control circuit comprises a cascaded arrangement of transistors that are sequentially controlled by the digital counter logic to conduct a varying portion of the activation current at each of the predetermined number of count values to adjust the amplitude of the activation voltage. 
     
     
         3 . The circuit of  claim 2 , wherein the digital counter logic is configured to generate a plurality of digital counter signals, and wherein the cascaded arrangement of transistors is arranged as a respective plurality of transistors that are controlled by the plurality of digital counter signals in a sequence based on the digital counter logic asserting the plurality of digital counter signals in a sequence based on the oscillator signal. 
     
     
         4 . A power supply system comprising the switch circuit of  claim 1 , the power supply system further comprising:
 a transformer comprising a primary winding configured to conduct the primary current and a secondary winding configured to generate a secondary current in response to the primary current; and   an output stage configured to generate an output voltage based on the secondary current.