Electronic chip manufacturing method

Abstract

Active areas of memory cells and active areas of transistors are delimited in an upper portion of a wafer. Floating gates are formed on active areas of the memory cells. A silicon oxide-nitride-oxide tri-layer is then deposited over the wafer and a protection layer is deposited over the silicon oxide-nitride-oxide tri-layer. Portions of the protection layer and tri-layer located over the active areas of transistors are removed. Dielectric layers are formed over the wafer and selectively removed from covering the non-removed portions of the protection layer and tri-layer. A memory cell gate is then formed over the non-removed portions of the protection layer and tri-layer and a transistor gate is then formed over the non-removed portions of the dielectric layers.

1 . An integrated circuit structure, comprising:
 a semiconductor substrate including isolation structures which delimit a plurality of active areas including a first active area for a first transistor, a second active area for a second transistor and a third active area for a memory cell;   a dielectric layer which extends over the first and second active areas to form at least part of a gate insulator for the first and second transistors;   a floating gate electrode for the memory cell over the third active area;   a silicon oxide-nitride-oxide trilayer covering an upper surface and side surfaces of the floating gate electrode;   a protection layer covering the silicon oxide-nitride-oxide trilayer; and   wherein the dielectric layer further extends over the protection layer.   
     
     
         2 . The structure of  claim 1 , wherein the protection layer is made of amorphous silicon. 
     
     
         3 . The structure of  claim 1 , wherein the protection layer is made of polysilicon. 
     
     
         4 . The structure of  claim 1 , wherein the dielectric layer contacts the silicon oxide-nitride-oxide trilayer only at a side edge of the silicon oxide-nitride-oxide trilayer. 
     
     
         5 . The structure of  claim 1 , wherein the dielectric layer has a first thickness over the first active area and a second thickness, different from the first thickness, over the second active area. 
     
     
         6 . The structure of  claim 1 , wherein the protection layer has a thickness in a range from 3 to 500 nm. 
     
     
         7 . The structure of  claim 1 , wherein the dielectric layer comprises:
 a silicon oxide layer; and   a layer made of a material of high permittivity over the silicon oxide layer.   
     
     
         8 . An integrated circuit structure, comprising:
 a semiconductor substrate including isolation structures which delimit a plurality of active areas including a first active area for a first transistor, a second active area for a second transistor and a third active area for a memory cell;   a dielectric layer which extends over the first and second active areas to form at least part of a gate insulator for the first and second transistors;   a floating gate electrode for the memory cell over the third active area;   a silicon oxide-nitride-oxide trilayer covering an upper surface and side surfaces of the floating gate electrode;   a control gate electrode for the memory cell over the silicon oxide-nitride-oxide trilayer;   a control gate electrode for the first transistor over the dielectric layer; and   a control gate electrode for the second transistor over the dielectric layer.   
     
     
         9 . The structure of  claim 8 , wherein the control gate electrodes for the memory cell, first transistor and second transistor are made of a same material and have a same thickness. 
     
     
         10 . The structure of  claim 8 , wherein the dielectric layer contacts the silicon oxide-nitride-oxide trilayer only at a side edge of the silicon oxide-nitride-oxide trilayer. 
     
     
         11 . The structure of  claim 8 , wherein the dielectric layer has a first thickness over the first active area and a second thickness, different from the first thickness, over the second active area. 
     
     
         12 . The structure of  claim 8 , wherein the dielectric layer comprises:
 a silicon oxide layer; and   a layer made of a material of high permittivity over the silicon oxide layer.   
     
     
         13 . An integrated circuit structure, comprising:
 a memory cell and a transistor supported by a substrate;   a silicon oxide-nitride-oxide tri-layer arranged over an active area for said memory cell and positioned between a floating gate of said memory cell and a control gate of said memory cell;   a material of high permittivity extending over an active area for said transistor; and   a control gate electrode for the transistor extending over the material of high permittivity.   
     
     
         14 . The structure of  claim 13 , further comprising a silicon oxide layer positioned between the material of high permittivity and the active area for said transistor. 
     
     
         15 . The structure of  claim 14 , wherein the silicon oxide layer contacts the silicon oxide-nitride-oxide trilayer only at a side edge of the silicon oxide-nitride-oxide trilayer.