Transfer of data with check bits

Abstract

A data transmitter is configured for transmitting multiple payload data streams in a frame format, wherein each frame comprises multiple rows, and each row comprises multiple bit slots. The data transmitter comprises: configuration storage circuitry, for storing frame format configuration data; an input, for receiving the multiple payload data streams; data multiplexing circuitry, for Combining the multiple payload data streams in accordance with the stored frame format configuration data to form a combined payload data stream; and redundancy code generator circuitry, for receiving the combined payload data stream, and generating check bit data therefrom. The data multiplexing circuitry is further configured for multiplexing the combined payload data stream and the check bit data into data for transmission in said frame format.

1 . A data transmitter for transmitting multiple payload data streams in a frame format, wherein each frame comprises multiple rows, and each row comprises multiple bit slots, the data transmitter comprising:
 configuration storage circuitry, for storing frame format configuration data;   an input, for receiving the multiple payload data streams;   data multiplexing circuitry, for combining the multiple payload data streams in accordance with the stored frame format configuration data to form a combined payload data stream; and   redundancy code generator circuitry, for receiving the combined payload data stream, and generating check bit data therefrom;   wherein the data multiplexing circuitry is further configured for multiplexing the combined payload data stream and the check bit data into data for transmission in said frame format.   
     
     
         2 . A data transmitter as claimed in  claim 1 , wherein the data multiplexing circuitry is further configured for multiplexing the combined payload data stream and the check bit data with at least one check bit in each row of the frame. 
     
     
         3 . A data transmitter as claimed in  claim 1 , wherein the data multiplexing circuitry is further configured for multiplexing the combined payload data stream and the check bit data into data for transmission, such that data of the multiple payload data streams appears at positions in the frame, as determined by the stored frame format configuration data. 
     
     
         4 . A data transmitter as claimed in  claim 1 , wherein the redundancy code generator circuitry is configured for generating the check bit data from the combined payload data stream by a recursive convolution process. 
     
     
         5 . A data transmitter as claimed in  claim 1 , wherein the redundancy code generator circuitry is clocked only once for each bit of the combined payload data stream, with generated check bits being stored until they are multiplexed into the data for transmission. 
     
     
         6 . A data transmitter as claimed in  claim 1 , wherein the redundancy code generator circuitry is clocked once for each bit of the combined payload data stream and once for each required check bit, with generated check bits being multiplexed into the data for transmission immediately on generation. 
     
     
         7 .- 8 . (canceled) 
     
     
         9 . A data transmitter as claimed in  claim 1 , wherein the frame format comprises synchronization bit slots, control data bit slots, and bits slots for receiving data during each row. 
     
     
         10 . A data transmitter as claimed in  claim 9 , comprising a clock recovery circuit for recovering a clock from received data. 
     
     
         11 .- 12 . (canceled) 
     
     
         13 . A data receiver for receiving data in a frame format, wherein each frame comprises multiple rows, and each row comprises multiple bit slots, the receiver comprising:
 configuration storage circuitry for storing frame format configuration data;   data selection circuitry, for extracting payload data and received check bit data from the received data according to the stored frame format configuration data;   a redundancy code generator, for generating from the payload data a stream of locally generated check bit data; and   data error checking circuitry, for comparing the locally generated check bit data with the extracted received check bit data, and for generating an error flag if the comparison identifies a difference between the locally generated check bit data and the extracted received check bit data.   
     
     
         14 . A data receiver as claimed in  claim 13 , wherein the data selection circuitry is further configured for extracting at least one check bit from each row of the frame. 
     
     
         15 . A data receiver as claimed in  claim 13 , wherein the data selection circuitry is further configured for extracting the multiple payload data streams from the combined payload data stream, and the multiple payload data streams appear at positions in the frame, as determined by the stored frame format configuration data. 
     
     
         16 . A data receiver as claimed in  claim 13 , wherein the redundancy code generator circuitry is configured for generating the check bit data from the combined payload data stream by a recursive convolution process. 
     
     
         17 . A data receiver as claimed in  claim 13 , wherein the redundancy code generator circuitry is clocked only once for each bit of the combined payload data stream, with generated check bits being stored until they are multiplexed into the data for transmission. 
     
     
         18 . A data receiver as claimed in  claim 13 , wherein the redundancy code generator circuitry is clocked once for each bit of the combined payload data stream and once for each required check bit. 
     
     
         19 . A data receiver as claimed in  claim 18 , wherein a known data value is input into the redundancy code generator circuitry during each bit period when a check bit is required. 
     
     
         20 .- 21 . (canceled) 
     
     
         22 . A data receiver as claimed in  claim 13 , comprising a clock recovery circuit for recovering a clock from received data. 
     
     
         23 .- 24 . (canceled) 
     
     
         25 . A data receiver as claimed in  claim 13 , wherein the receiver outputs the extracted payload data for processing, and wherein the processing is controlled in response to generation of an error flag. 
     
     
         26 .- 28 . (canceled) 
     
     
         29 . A data receiver as claimed in  claim 13 , wherein the receiver outputs the extracted payload data for processing, and wherein the processing is performed with a deliberate delay of at least one bit clock period to allow for comparing at least one bit of the locally generated check bit data with the extracted received check bit data before the processing. 
     
     
         30 . A data receiver as claimed in  claim 29 , wherein the receiver outputs the extracted payload data for processing, and wherein the processing is performed with a deliberate delay of at least one row period to allow for comparing multiple bits of the locally generated check bit data with the extracted received check bit data before the processing. 
     
     
         31 . A data transmission system, comprising:
 a data transmitter for transmitting multiple payload data streams in a frame format, wherein each frame comprises multiple rows, and each row comprises multiple bit slots, the data transmitter comprising:
 configuration storage circuitry, for storing frame format configuration data; 
 an input, for receiving the multiple payload data streams; 
 data multiplexing circuitry, for combining the multiple payload data streams in accordance with the stored frame format configuration data to form a combined payload data stream; and 
 redundancy code generator circuitry, for receiving the combined payload data stream, and generating check bit data therefrom; 
 wherein the data multiplexing circuitry is further configured for multiplexing the combined payload data stream and the check bit data into data for transmission in said frame format; and 
   a data receiver for receiving data in a frame format, wherein each frame comprises multiple rows, and each row comprises multiple bit slots, the receiver comprising:
 configuration storage circuitry for storing frame format configuration data; 
 data selection circuitry, for extracting payload data and received check bit data from the received data according to the stored frame format configuration data; 
 a redundancy code generator, for generating from the payload data a stream of locally generated check bit data; and 
 data error checking circuitry, for comparing the locally generated check bit data with the extracted received check bit data, and for generating an error flag if the comparison identifies a difference between the locally generated check bit data and the extracted received check bit data; 
   wherein the data transmitter and the data receiver are coupled by a wired link.   
     
     
         32 .- 57 . (canceled)