US2018319108A1PendingUtilityA1

Methods of fabricating electronic and mechanical structures

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Assignee: NUVOTRONICS INCPriority: Jul 13, 2011Filed: Jun 7, 2018Published: Nov 8, 2018
Est. expiryJul 13, 2031(~5 yrs left)· nominal 20-yr term from priority
H05K 2201/037H05K 1/0284H05K 1/0274B22D 19/00H05K 3/1275H05K 2201/0191H05K 2201/0195C25D 5/02H05K 3/4664B33Y 80/00B29C 64/00B29C 70/882B29C 64/106B29C 67/00H01P 11/005H01P 3/06
51
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Claims

Abstract

The present invention relates to the fabrication of complicated electronic and/or mechanical structures and devices and components using homogeneous or heterogeneous 3D additive build processes. In particular the invention relates to selective metallization processes including electroless and/or electrolytic metallization.

Claims

exact text as granted — not AI-modified
1 - 20 . (canceled) 
     
     
         21 . A method of fabricating a 3D structure, comprising:
 providing a substrate having at least one integrated circuit disposed thereon;   depositing onto the substrate using 3D printing a first dielectric material to create a first patterned layer having at least one region in which the first dielectric material is deposited and at least one void region in which no first dielectric material is deposited;   depositing, on the first patterned layer, a second dielectric material to create a second patterned layer having at least one region in which the second dielectric material is deposited and at least one void region in which no second dielectric material is deposited; and   depositing a metal into selected portions of one or both of the at least one void regions of the first and second patterned layers, thereby providing a 3D structure.   
     
     
         22 . The method of  claim 21 , wherein the 3D structure is an electronic structure. 
     
     
         23 . The method of  claim 21 , wherein the substrate comprises a circuit board. 
     
     
         24 . The method of  claim 21 , wherein the substrate comprises a nonplanar surface. 
     
     
         25 . The method of  claim 21 , wherein one or both of the first and second patterned layers have portions of differing thickness. 
     
     
         26 . The method of  claim 21 , wherein the first and second dielectric materials comprise the same material. 
     
     
         27 . The method of  claim 21 , wherein the first and second dielectric materials comprise different materials. 
     
     
         28 . The method of  claim 21 , wherein one or both of the first and second dielectric materials comprise a photoimageable material. 
     
     
         29 . The method of  claim 28 , comprising patterning the photoimageable material using a photolithographic technique. 
     
     
         30 . The method of  claim 21 , wherein one or both of the first and second dielectric materials comprise a metallization catalyst disposed therethrough. 
     
     
         31 . The method of  claim 30 , comprising etching the dielectric material comprising the metallization catalyst to increase the number of catalyst sites in a surface thereof. 
     
     
         32 . The method of  claim 30 , comprising exposing the first and second dielectric materials with metal-containing material to selectively deposit metal on the dielectric material containing the metallization catalyst. 
     
     
         33 . The method of  claim 32 , wherein the metal-containing material comprises a gas or a vapor. 
     
     
         34 . The method of  claim 21 , wherein only one of the first and second dielectric materials comprise a metallization catalyst disposed therethrough. 
     
     
         35 . The method of  claim 34 , comprising exposing the first and second dielectric materials with a process that selectively deposits metal on the dielectric containing the metallization catalyst while not depositing metal on the other dielectric material. 
     
     
         36 . The method of  claim 35 , wherein the process comprises atomic layer deposition. 
     
     
         37 . The method of  claim 21 , comprising removing one or both of the first and second dielectric materials. 
     
     
         38 . The method of  claim 21 , comprising milling one or both of the first and second layers to planarize the surface of the layer. 
     
     
         39 . The method of  claim 21 , wherein the step of depositing the metal comprises deposition by electroless metallization. 
     
     
         40 . The method of  claim 39 , wherein the metal comprises copper. 
     
     
         41 . The method of  claim 21 , wherein the step of depositing the metal comprises deposition by electrolytic plating. 
     
     
         42 . The method of  claim 41 , wherein the metal comprises copper. 
     
     
         43 . The method of  claim 21 , wherein the metal comprises copper. 
     
     
         44 . A method of fabricating a 3D structure, comprising:
 providing a substrate having at least one integrated circuit disposed thereon;   depositing onto the substrate using 3D printing a first dielectric material to create a patterned layer having at least one region in which the first dielectric material is deposited and at least one void region in which no first dielectric material is deposited;   depositing, on the first patterned layer, a second dielectric material different from the first dielectric material to create a second patterned layer having at least one region in which the second dielectric material is deposited and at least one void region in which no second dielectric material is deposited; and   exposing the first and second dielectric materials with a process that selectively deposits metal on only one of the first and second dielectric materials.

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