Thyristor Memory Cell with Assist Device

Abstract

A vertical thyristor memory array including: a vertical thyristor memory cell, the vertical thyristor memory cell including: a p+ anode; an n-base located below the p+ anode; a p-base located below the n-base; a n+ cathode located below the p-base; an isolation trench located around the vertical thyristor memory cell; an assist gate located in the isolation trench adjacent the n-base wherein an entire vertical height of the assist gate is positioned within an entire vertical height of the n-base.

The invention claimed is: 
     
         1 . A vertical thyristor memory array comprising:
 a vertical thyristor memory cell, the vertical thyristor memory cell comprising:   a p+ anode;   an n-base disposed below the p+ anode;   a p-base disposed below the n-base;   a n+ cathode disposed below the p-base;   an isolation trench disposed around the vertical thyristor memory cell;   an assist gate disposed in the isolation trench adjacent the n-base wherein an entire vertical height of the assist gate is disposed within an entire vertical height of the n-base.   
     
     
         2 . The vertical thyristor memory array of  claim 1  wherein the assist gate comprises P-type coupling capacitor. 
     
     
         3 . The vertical thyristor memory array of  claim 1  wherein the assist gate runs orthogonal to the anode lines. 
     
     
         4 . The vertical thyristor memory array of  claim 1  wherein the assist gate runs parallel to the anode lines. 
     
     
         5 . A vertical thyristor memory array comprising:
 A vertical thyristor memory cell, the vertical thyristor memory cell comprising:   a p+ anode;   an n-base disposed below the p+ anode;   a p-base disposed below the n-base;   a n+ cathode disposed below the p-base;   an isolation trench disposed around the vertical thyristor memory cell;   an assist gate disposed in the isolation trench adjacent the p-base wherein an entire vertical height of the assist gate is disposed within an entire vertical height of the p-base.   
     
     
         6 . The vertical thyristor memory array of  claim 3  wherein the assist gate comprises NMOS. 
     
     
         7 . The vertical thyristor memory array of  claim 1  wherein the assist gate runs parallel to the anode lines. 
     
     
         8 . The vertical thyristor memory array of  claim 1  wherein the assist gate runs parallel to the anode lines.