Low power scheme for bit flipping low density parity check decoder

Abstract

A method for dynamically adapting a clock frequency used to perform low-density parity check (LDPC) decoding includes: setting a first clock frequency for performing a first LDPC decoding iteration on a received codeword to generate a decoded codeword; performing a successive plurality of LDPC decoding iterations on the decoded codeword; at the end of each LDPC decoding iteration, determining a number of error bits of the decoded codeword and a throughput of the LDPC decoding iteration; and when a number of the error bits increases, increasing the clock frequency for performing a next LDPC decoding iteration so that a throughput of the next LDPC decoding iteration is the same as the throughput of the immediately preceding iteration. The first clock frequency is set according to a number of error bits in an immediately previous decoding operation.

What is claimed is: 
     
         1 . A method for dynamically adapting a clock frequency used to perform low-density parity check (LDPC) decoding, the method comprising:
 setting a first clock frequency for performing a first LDPC decoding iteration on a received codeword to generate a decoded codeword;   performing a successive plurality of LDPC decoding iterations on the decoded codeword;   at the end of each LDPC decoding iteration, determining a number of error bits of the decoded codeword and a throughput of the LDPC decoding iteration; and   when a number of the error bits increases, increasing the clock frequency for performing a next LDPC decoding iteration so that a throughput of the next LDPC decoding iteration is the same as the throughput of the immediately preceding iteration.   
     
     
         2 . The method of  claim 1 , wherein the LDPC decoding is hard decision decoding using a bit flipping algorithm, and the method further comprises:
 at the end of each decoding iteration, determining a syndrome weight;   monitoring the syndrome weights over the plurality of decoding iterations;   when the syndrome weights begin to overlap, performing a final decoding iteration using the bit flipping algorithm; and   increasing the clock frequency and switching the decoding mode to hard decision soft decoding mode.   
     
     
         3 . The method of  claim 1 , wherein the first clock frequency is set according to a number of error bits in an immediately previous decoding operation. 
     
     
         4 . A low-density parity check (LDPC) decoder which dynamically adapts a clock frequency used to perform decoding, the LDPC decoder comprising:
 an oscillator, for providing a clock to the LDPC decoder for a plurality of decoding iterations, wherein a first clock frequency of the oscillator is set for performing a first LDPC decoding iteration of the plurality of decoding iterations on a received codeword to generate a decoded codeword;   a check syndrome weight circuit, for determining a number of error bits of the decoded codeword at the end of each decoding iteration; and   a processor, coupled to the oscillator and the check syndrome weight circuit, for controlling operations of the LDPC decoder, wherein the processor determines a throughput of each LDPC decoding iteration, and when a number of the error bits increases, the processor increases the clock frequency for performing a next LDPC decoding iteration of the plurality of decoding iterations so that a throughput of the next LDPC decoding iteration is the same as the throughput of an immediately preceding iteration.   
     
     
         5 . The LDPC decoder of  claim 4 , wherein the LDPC decoding is hard decision decoding using a bit flipping algorithm, the check syndrome weight circuit further determines a syndrome weight at the end of each decoding iteration, the processor further monitors the syndrome weights over the plurality of decoding iterations, and when the syndrome weights begin to overlap, the processor controls the LDPC decoder to perform a final decoding iteration using the bit flipping algorithm, controls the oscillator to increase the clock frequency, and controls the LDPC decoder to switch the decoding mode to hard decision soft decoding mode. 
     
     
         6 . The LDPC decoder of  claim 4 , wherein the first clock frequency is set according to a number of error bits in an immediately previous decoding operation.