Power MOSFET Having Improved Manufacturability, Low On-Resistance and High Breakdown Voltage

Abstract

Stripe-shaped surface transistor structures of a power MOSFET are disposed over an array of parallel-extending P type Buried Stripe-Shaped Charge Compensation Regions (BSSCCRs). The power MOSFET has two and only two epitaxial semiconductor layers, and the BSSCCRs are disposed at the interface between these layers. Looping around the area occupied by these parallel-extending BSSCCRs is a P type ring-shaped BSSCCR. At the upper semiconductor surface are disposed three P type surface rings. The inner surface ring and outer surface ring are coupled together by a bridging metal member, but the center surface ring is floating. The bridging metal member is disposed at least in part over the ring-shaped BSSCCR. The MOSFET has a high breakdown voltage, a low R DS(ON) , and is acceptable and suitable for manufacture at semiconductor fabrication. plants that cannot or typically do not make superjunction MOSFETs.

1 - 18 . (canceled) 
     
     
         19 . A power field effect transistor die structure comprising:
 a substrate semiconductor layer of a first conductivity type;   a first epitaxial semiconductor layer disposed on the substrate;   a second epitaxial semiconductor layer disposed on the first epitaxial semiconductor layer, wherein an upper surface of the second epitaxial semiconductor layer is an upper semiconductor surface of the die structure, and wherein the first and second epitaxial semiconductor layers are the only epitaxial semiconductor layers of the power field effect transistor die structure;   a plurality of buried charge compensation regions of a second conductivity type, wherein each of the buried charge compensation regions of the plurality of buried charge compensation regions is disposed partly in the first epitaxial layer and is disposed partly in the second epitaxial layer but is entirely covered by semiconductor material of the first conductivity type of the second epitaxial semiconductor layer;   a transistor structure that is disposed over the plurality of buried charge compensation regions, wherein the transistor structure includes a gate region and a source region;   an inner buried charge compensation region of the second conductivity type, wherein the inner buried charge compensation region extends adjacent a periphery of the plurality of buried charge compensation regions, wherein the inner buried charge compensation region is disposed partly in the first epitaxial layer and is disposed partly in the second epitaxial layer but is entirely covered by semiconductor material of the first conductivity type of the second epitaxial semiconductor layer;   an outer buried charge compensation region of the second conductivity type that extends parallel to the inner buried charge compensation region such that the inner buried charge compensation region is disposed between the outer buried charge compensation region and the plurality of buried charge compensation regions, wherein the outer buried charge compensation region is disposed partly in the first epitaxial layer and is disposed partly in the second epitaxial layer but is entirely covered by semiconductor material of the first conductivity type of the second epitaxial semiconductor layer;   a first surface region of the second conductivity type, wherein the first surface region is disposed at the upper semiconductor surface of the die structure;   a second surface region of the second conductivity type, wherein the second surface region extends parallel to the first surface region at the upper semiconductor surface of the die structure, and wherein the second surface region is floating and is stripe-shaped;   a third surface region of the second conductivity type, wherein the third surface region extends parallel to the second surface region at the upper semiconductor surface of the die structure such that the second surface region is disposed between the first and third surface regions, wherein the third surface region is stripe-shaped;   a drain metal electrode;   a source metal electrode;   a gate metal electrode; and   a metal bridging member that electrically couples the first and third surface regions together, wherein the metal bridging member bridges over the second surface region but is not physically contacting the second surface region, wherein the metal bridging member is disposed at least in part over the inner buried charge compensation region, and wherein the metal bridging member does not contact or adjoin either the source metal electrode or the gate metal electrode.   
     
     
         20 . The power field effect transistor die structure of  claim 19 , wherein all the buried charge compensation regions of the plurality of buried charge compensation regions are floating, wherein the inner buried charge compensation region is floating, wherein the outer buried charge compensation region is floating, and wherein there is no semiconductor region of the second conductivity type disposed between the first and third surface regions other than the second surface region. 
     
     
         21 . The power field effect transistor die structure of  claim 19 , wherein the source metal electrode contacts a body region of the second conductivity type at the upper semiconductor surface of the die structure, wherein an active area of the power field effect transistor die structure has a specific on-resistance (R ON,SP ) of not more than 0.8 milliohms-cm 2  when the power field effect transistor die structure is on, and wherein the power field effect transistor die structure has a drain-to-source breakdown voltage of at least one hundred volts. 
     
     
         22 . The power field effect transistor die structure of  claim 19 , wherein the second surface region is a ring, and wherein the third surface region is a ring that surrounds the second surface region. 
     
     
         23 . The power field effect transistor die structure of  claim 19 , wherein each of the plurality of buried charge compensation regions has an end, and wherein there is no buried P type semiconductor region disposed between any end of any of the plurality of buried charge compensation regions and the inner buried charge compensation region. 
     
     
         24 . The power field effect transistor die structure of  claim 19 , wherein the power field effect transistor die structure includes no transistor gate region that is disposed outside the first surface region. 
     
     
         25 . The power field effect transistor die structure of  claim 19 , wherein each of the plurality of buried charge compensation regions has a cross-sectional width and a cross-sectional height, wherein the cross-sectional height is greater than the cross-sectional width. 
     
     
         26 . The power field effect transistor die structure of  claim 19 , wherein the first epitaxial semiconductor layer comprises an N− type layer portion and an N type layer portion, wherein the N− type layer portion of the first epitaxial semiconductor layer is disposed on the substrate semiconductor layer, and wherein the N type layer portion of the first epitaxial semiconductor layer is disposed on the N− type layer portion of the first epitaxial semiconductor layer. 
     
     
         27 . The power field effect transistor die structure of  claim 19 , wherein the second epitaxial semiconductor layer comprises an N− type layer portion and an N type layer portion, wherein the N type layer portion of the second epitaxial semiconductor layer is disposed on the first epitaxial semiconductor layer, and wherein the N− type layer portion of the second epitaxial semiconductor layer is disposed on the N type layer portion of the second epitaxial semiconductor layer. 
     
     
         28 . The power field effect transistor die structure of  claim 19 , wherein the second surface region is disposed at least in part over the inner buried charge compensation region. 
     
     
         29 . The power field effect transistor die structure of  claim 19 , wherein the transistor structure is taken from the group consisting of: 1) an array of stripe trench transistor devices, and 2) an array of stripe planar transistor devices. 
     
     
         30 . The power field effect transistor die structure of  claim 19 , wherein the gate metal electrode extends over an end portion of one of the plurality of buried charge compensation regions. 
     
     
         31 . A die structure comprising:
 a substrate semiconductor layer of a first conductivity type;   a first epitaxial semiconductor layer disposed on the substrate;   a second epitaxial semiconductor layer disposed on the first epitaxial semiconductor layer, wherein an upper surface of the second epitaxial semiconductor layer is an upper semiconductor surface of the die structure;   a plurality of buried charge compensation regions of a second conductivity type, wherein each of the buried charge compensation regions of the plurality of buried charge compensation regions is disposed partly in the first epitaxial layer and is disposed partly in the second epitaxial layer;   an inner buried charge compensation region of the second conductivity type, wherein the inner buried charge compensation region extends adjacent a periphery of the plurality of buried charge compensation regions, and wherein the inner buried charge compensation region is disposed partly in the first epitaxial layer and is disposed partly in the second epitaxial layer; and   an outer buried charge compensation region of the second conductivity type that extends parallel to the inner buried charge compensation region such that the inner buried charge compensation region is disposed between the outer buried charge compensation region and the plurality of buried charge compensation regions, wherein the outer buried charge compensation region is disposed partly in the first epitaxial layer and is disposed partly in the second epitaxial layer.   
     
     
         32 . The die structure of  claim 31 , wherein the die structure does not include any epitaxial semiconductor layers other than the first and second epitaxial semiconductor layers. 
     
     
         33 . The die structure of  claim 31 , wherein each of the plurality of buried charge compensation regions has an end, and wherein there is no buried P type semiconductor region disposed between any end of any of the plurality of buried charge compensation regions and the inner buried charge compensation region. 
     
     
         34 . The die structure of  claim 31 , wherein each of the plurality of buried charge compensation regions has a cross-sectional width and a cross-sectional height, and wherein the cross-sectional height is greater than the cross-sectional width. 
     
     
         35 . The die structure of  claim 31 , wherein the first epitaxial semiconductor layer comprises an N− type layer portion and an N type layer portion, wherein the N− type layer portion of the first epitaxial semiconductor layer is disposed on the substrate semiconductor layer, wherein the N type layer portion of the first epitaxial semiconductor layer is disposed on the N− type layer portion of the first epitaxial semiconductor layer, wherein the second epitaxial semiconductor layer comprises an N− type layer portion and an N type layer portion, wherein the N type layer portion of the second epitaxial semiconductor layer is disposed on the first epitaxial semiconductor layer, and wherein the N− type layer portion of the second epitaxial semiconductor layer is disposed on the N type layer portion of the second epitaxial semiconductor layer. 
     
     
         36 . A power field effect transistor die structure comprising:
 a drain metal electrode;   a source metal electrode;   a gate metal electrode;   a substrate semiconductor layer of a first conductivity type;   a first epitaxial semiconductor layer disposed on the substrate;   a second epitaxial semiconductor layer disposed on the first epitaxial semiconductor layer, wherein an upper surface of the second epitaxial semiconductor layer is an upper semiconductor surface of the die structure;   a plurality of buried charge compensation regions of a second conductivity type, wherein each of the buried charge compensation regions of the plurality of buried charge compensation regions is disposed partly in the first epitaxial layer and is disposed partly in the second epitaxial layer;   an inner buried charge compensation region of the second conductivity type, wherein the inner buried charge compensation region extends adjacent a periphery of the plurality of buried charge compensation regions, wherein the inner buried charge compensation region is disposed partly in the first epitaxial layer and is disposed partly in the second epitaxial layer;   an outer buried charge compensation region of the second conductivity type that extends parallel to the inner buried charge compensation region such that the inner buried charge compensation region is disposed between the outer buried charge compensation region and the plurality of buried charge compensation regions, wherein the outer buried charge compensation region is disposed partly in the first epitaxial layer and is disposed partly in the second epitaxial layer; and   a metal bridging member that electrically couples two surface regions of the second conductivity type together, wherein the two surface regions are disposed at the upper semiconductor surface of the die structure, and wherein the metal bridging member is disposed at least in part over the inner buried charge compensation region.   
     
     
         37 . The power field effect transistor die structure of  claim 36 , wherein the metal bridging member bridges over a floating surface region, wherein the metal bridging member does not physically contact the floating surface region, and wherein the floating surface region is disposed at the upper semiconductor surface of the die structure.