Configurable power management integrated circuit

Abstract

In accordance with aspects of the present invention, a programmable power management integrated circuit is presented. An integrated circuit can include a plurality of cells, each cell including at least one driver for a switchable element; and a switch matrix and controller coupled to the plurality of cells, the switch matrix and controller being programmable to configure at least one power channel, each power channel including at least one cell of the plurality of cells. A method of providing a power management system using the integrated circuit includes receiving power requirements corresponding to a target device; providing implementation options to achieve the power requirements; selecting a solution from the implementation options; generating a programming file for a power management integrated circuit, and generating a printed circuit board design for the power management integrated circuit.

1 . A power management integrated circuit, comprising:
 a plurality of cells, each cell including at least one driver for a pair of series-coupled switching elements; and   a switch matrix and controller coupled to the plurality of cells, the switch matrix and controller configured to couple one or more of the plurality of cells in combinations of series and parallel configurations to form one or more individual power channels in response to programming signals, each power channel including at least one cell of the plurality of cells.   
     
     
         2 . The circuit of  claim 1 , wherein each power channel is configured to couple to components mounted on a printed circuit board with the power management integrated circuit to provide a rail to a target device. 
     
     
         3 . (canceled) 
     
     
         4 . The circuit of  claim 1 , wherein at least one of the plurality of cells includes one of the at least one drivers and a switchable element driven by the driver. 
     
     
         5 . The circuit of  claim 1 , wherein the at least one driver includes an amplifier and a slew-rate adjust circuit. 
     
     
         6 . The circuit of  claim 1 , wherein an output signal from the driver is switchably output to an I/O pin of the integrated circuit. 
     
     
         7 . The circuit of  claim 4 , wherein an output signal from the drive is coupled to an external switching device. 
     
     
         8 . The circuit of  claim 7 , wherein the switching device is an FET, the source and drain of which are coupled to I/O pins of the integrated circuit. 
     
     
         9 . The circuit of  claim 8 , wherein the FET includes a plurality of individual FETs and the FET can be programmed to include any of the plurality of individual FETs. 
     
     
         10 . The circuit of  claim 7 , further including a programmable element that is configurable to couple the output signal from the driver to an I/O pin or to couple the output signal from the driver to the switching device. 
     
     
         11 . The circuit of  claim 1 , wherein each of the plurality of elements is configurable to adjust performance of the element. 
     
     
         12 . The circuit of  claim 1 , wherein each cell includes a higher element and a lower element. 
     
     
         13 . The circuit of  claim 12 , wherein the higher element includes a high driver coupled to a high FET and the lower element includes a low driver coupled to a low FET. 
     
     
         14 . The circuit of  claim 13 , wherein the lower element is a diode. 
     
     
         15 . The circuit of  claim 13 , wherein the higher element is a diode. 
     
     
         16 . The circuit of  claim 13 , wherein the high FET and the low FET are coupled in series to provide an output signal between the high FET and the low FET. 
     
     
         17 . The circuit of  claim 16 , wherein the output signals from multiple cells are combined to complete a buck converter. 
     
     
         18 . The circuit of  claim 16 , wherein the output signals from multiple cells are combined to complete a buck/boost converter. 
     
     
         19 . The circuit of  claim 16 , wherein multiple cells are coupled as a cascode. 
     
     
         20 . The circuit of  claim 12 , wherein the switch matrix and control block includes a plurality of controllers coupled to a switch matrix. 
     
     
         21 . The circuit of  claim 20 , wherein the switch matrix is programmable to establish one or more power channels, each power channel including one or more cells, a switching matrix, and an assigned controller. 
     
     
         22 . The circuit of  claim 21 , wherein the switch matrix for each power channel includes:
 a high programmable logic circuit that determines whether a high element gate voltage of one or more of the high FETs of cells included in the power channel is a high voltage;   a low programmable logic circuit that determines whether a low element gate voltage of one or more of the low FETs of cells included in the power channel is a high voltage;   a non-overlap circuit that receives a high logic signal from the high programmable logic circuit, a low logic signal from the low programmable logic circuit, and a pulse-wave signal from the assigned controller from the plurality of controllers and provides a high gate signal and a low gate signal;   a high gate output circuit that provides a high gate signal to the high element of each cell included in the power channel; and   a low gate output circuit that provides a low gate signal to the low element of each cell included in the power channel.   
     
     
         23 . The circuit of  claim 22 , wherein the switching matrix further includes a multiplexer that receives pulse-wave signals from more than one of the plurality of controllers, the multiplexer capable of dynamically selecting from the more than one controller to provide the pulse-wave signal to the non-overlap block. 
     
     
         24 . The circuit of  claim 21 , wherein the controller includes:
 an error amplifier that receives a feedback signal from the output signal from the power channel and provides an error signal;   a ramp generator that provides a ramp voltage;   a comparator that compares the ramp voltage with the error signal to form a compared signal;   an oscillator that provides a pulse signal;   a logic circuit that receives the pulse signal and the compare signal and provides a logic signal; and   a flip-flop that receives the logic signal and provides a pulse-wave signal to the switch matrix.   
     
     
         25 . The circuit of  claim 24 , wherein the controller further includes a voltage reference generator that generates a reference voltage for the error amplifier. 
     
     
         26 . The circuit of  claim 24 , wherein the logic circuit receives an on-time pulse and an off-time pulse from the oscillator. 
     
     
         27 . The circuit of  claim 24 , wherein the controller further includes a thermal sensor input to the logic circuit. 
     
     
         28 . The circuit of  claim 24 , wherein the controller further includes an over-current protection signal input to the logic circuit. 
     
     
         29 . The circuit of  claim 23 , wherein the control circuit includes a processor operating a state machine. 
     
     
         30 . The circuit of  claim 29 , wherein the state machine includes a configuration state where programming instructions are received for each power channel. 
     
     
         31 . The circuit of  claim 29 , wherein the state machine includes a channel state machine for each of the power channels, the channel state machine including:
 an idle state where a feedback signal is zero and the circuit is not enabled;   a soft-start state that is transitioned to from the idle state when the circuit becomes enabled, the soft-start state operating the circuit to raise the feedback signal to a reference value;   a run state that is transitioned to from the soft-start state when the feedback signal is the reference signal, the run state operating the circuit to produce power on the power channel; and   a shut-down state that is transitioned to whenever the circuit becomes not enabled or an error condition is detected.   
     
     
         32 . The circuit of  claim 1 , wherein the circuit includes programmable elements that are programmed to device the at least one power channel. 
     
     
         33 . The circuit of  claim 32 , wherein the programmable elements include one or more of non-volatile memory, registers, and fuses. 
     
     
         34 . The circuit of  claim 33 , wherein the programmable elements are programmed to determine operation of each power channel in the circuit. 
     
     
         35 - 38 . (canceled)