Low-cost packaging for fluidic and device co-integration

Abstract

The present disclosure provides methods for packaging a chip and packaged chips in which the chip and packaging are co-planar and gap-less. In certain instances, the packaged chip has electrodes or fluidics integrated with the chip.

1 .- 105 . (canceled) 
     
     
         106 . A packaged chip, comprising:
 a chip having a first surface and a second surface;   a carrier surrounding and bonded to the chip, wherein the first surface of the chip is substantially planar with respect to a surface of the carrier; and   global alignment features on the carrier, which global alignment features are aligned to the chip.   
     
     
         107 . The packaged chip of  claim 106 , wherein the global alignment features comprise a dowel or a hole. 
     
     
         108 . The packaged chip of  claim 106 , wherein a gap between the planarizing surface and the first surface of the chip and the carrier is less than about 10 micron (μm). 
     
     
         109 . The packaged chip of  claim 106 , wherein the chip further comprises a local alignment feature. 
     
     
         110 . The packaged chip of  claim 106 , wherein the carrier is bonded to the chip without a gap. 
     
     
         111 . The packaged chip of  claim 106 , wherein the chip comprises an integrated circuit (IC), a light-emitting diode (LED), or a micro-electromechanical system (MEMS). 
     
     
         112 . The packaged chip of  claim 106 , wherein the chip is not attached to a printed circuit board. 
     
     
         113 . The packaged chip of  claim 106 , further comprising a fluidic cap attached to the carrier and aligned to the global alignment features. 
     
     
         114 . The packaged chip of  claim 113 , wherein the fluidic cap comprises a dowel, the carrier comprises a hole, and the dowel is fit into the hole to align the fluidic cap to the carrier. 
     
     
         115 . The packaged chip of  claim 113 , wherein the fluidic cap comprises a hole, the carrier comprises a dowel, and the dowel is fit into the hole to align the fluidic cap to the carrier. 
     
     
         116 . The packaged chip of  claim 113 , wherein the fluidic cap comprises a first hole, the carrier comprises a second hole, and a dowel is fit into the first hole and the second hole to align the fluidic cap to the carrier. 
     
     
         117 . The packaged chip of  claim 113 , further comprising a first fiducial mark on the fluidic cap that is aligned to a second fiducial mark on the carrier or the chip. 
     
     
         118 . The packaged chip of  claim 113 , wherein the fluidic cap comprises a microfluidic channel, a mixer or a droplet generator. 
     
     
         119 . The packaged chip of  claim 113 , wherein the fluidic cap is attached to the carrier by at least partially melting or dissolving the fluidic cap or the carrier. 
     
     
         120 . The packaged chip of  claim 106 , further comprising an electrode aligned to the global alignment features and in electrical contact with the chip. 
     
     
         121 . The packaged chip of  claim 120 , wherein the electrode is not wire bonded to the chip. 
     
     
         122 . The packaged chip of  claim 113 , further comprising a first fiducial mark on a shadow mask that is aligned to a second fiducial mark on the carrier or the chip. 
     
     
         123 . The packaged chip of  claim 120 , wherein the electrode is in electrical communication with a contact pad on the chip. 
     
     
         124 . The packaged chip of  claim 106 , wherein an additional chip is aligned to the global alignment features on the carrier.