Method and/or apparatus for frame accurate hot failover

Abstract

A method for switching between two redundant bitstreams. The first bitstream may be presented to a first pipeline. The second bitstream may be presented to a second pipeline. The first bitstream and the second bitstream may contain redundant information received from independent sources. If the first bitstream fails, the method may present an output of the second pipeline to the output pipeline. Data in a buffer in the second pipeline may be used to pass a next frame to the output pipeline. A size of a buffer of the first pipeline and a size of the buffer in the second pipeline may be adjusted based on a time of reception of the first and the second bitstream.

1 . A computer-implemented method comprising:
 receiving a first bitstream for a first pipeline and a second bitstream for a second pipeline;   sending an output of the first pipeline to an output pipeline;   determining an error has occurred in the first pipeline; and   sending an output that is associated with an adjustment frame of the second pipeline to the output pipeline.   
     
     
         2 . The computer-implemented method of  claim 1 , wherein the first bitstream and the second bitstream comprise redundant information received from independent sources. 
     
     
         3 . The computer-implemented method of  claim 1 , further comprising:
 adjusting a first size of a first buffer of the first pipeline and a second size of a second buffer of the second pipeline based at least on timing information associated with the first bitstream and the second bitstream.   
     
     
         4 . The computer-implemented method of  claim 1 , further comprising:
 identifying a first timecode associated with a last frame sent to the output pipeline from the first pipeline;   identifying a second timecode associated with a next frame in a buffer associated with the second pipeline;   determining the second timecode is less than or equal to the first timecode; and   dropping the next frame.   
     
     
         5 . The computer-implemented method of  claim 1 , further comprising:
 identifying a first timecode associated with a last frame sent to the output pipeline from the first pipeline;   identifying a second timecode associated with a next frame in a buffer associated with the second pipeline;   determining the second timecode is greater than the first timecode; and   sending the next frame to the output pipeline.   
     
     
         6 . The computer-implemented method of  claim 1 , further comprising:
 identifying a first timecode associated with a last frame sent to the output pipeline from the first pipeline;   identifying a second timecode associated with a next frame in a buffer associated with the second pipeline;   determining the second timecode is greater than the first timecode; and   increasing the size of the buffer based at least on a difference between the second timecode and the first timecode.   
     
     
         7 . The computer-implemented method of  claim 1 , further comprising:
 identifying a first timecode associated with a last frame sent to the output pipeline from the first pipeline;   identifying a second timecode associated with a next frame in a buffer associated with the second pipeline;   determining the second timecode is less than the first timecode; and   decreasing the size of the buffer based at least on a difference between the second timecode and the first timecode.   
     
     
         8 . The computer-implemented method of  claim 1 , further comprising:
 identifying a first timecode associated with a last frame sent to the output pipeline from the first pipeline;   identifying a second timecode associated with a next frame in a buffer associated with the second pipeline;   determining the second timecode is equal to the first timecode; and   maintaining the size of the buffer.   
     
     
         9 . The computer-implemented method of  claim 1 , wherein the first pipeline and the second pipeline are each configured to perform one or more of demultiplexing, decoding, or buffering. 
     
     
         10 . The computer-implemented method of  claim 1 , wherein the output pipeline comprises an output buffer having a size based at least on an output bitrate and a time to switch from the output of the first pipeline and the output of the second pipeline. 
     
     
         11 . A system comprising:
 at least one processor; and   at least one computer readable storage medium including instructions stored thereon which, when executed, cause the system to:   receive a first bitstream for a first pipeline and a second bitstream for a second pipeline;   send an output of the first pipeline to an output pipeline;   determine an error has occurred in the first pipeline; and   send an output that is associated with an adjustment frame of the second pipeline to the output pipeline.   
     
     
         12 . The system of  claim 11 , wherein the instructions, when executed, further cause the system to:
 adjust a first size of a first buffer of the first pipeline and a second size of a second buffer of the second pipeline based at least on timing information associated with the first bitstream and the second bitstream.   
     
     
         13 . The system of  claim 11 , wherein the instructions, when executed, further cause the system to:
 identify a first timecode associated with a last frame sent to the output pipeline from the first pipeline;   identify a second timecode associated with a next frame in a buffer associated with the second pipeline;   determine the second timecode is less than or equal to the first timecode; and   drop the next frame.   
     
     
         14 . The system of  claim 11 , wherein the instructions, when executed, further cause the system to:
 identify a first timecode associated with a last frame sent to the output pipeline from the first pipeline;   identify a second timecode associated with a next frame in a buffer associated with the second pipeline;   determine the second timecode is greater than the first timecode; and   send the next frame to the output pipeline.   
     
     
         15 . The system of  claim 11 , wherein the instructions, when executed, further cause the system to:
 identify a first timecode associated with a last frame sent to the output pipeline from the first pipeline;   identify a second timecode associated with a next frame in a buffer associated with the second pipeline;   determine the second timecode is greater than the first timecode; and   increase the size of the buffer based at least on a difference between the second timecode and the first timecode.   
     
     
         16 . The system of  claim 11 , wherein the instructions, when executed, further cause the system to:
 identify a first timecode associated with a last frame sent to the output pipeline from the first pipeline;   identify a second timecode associated with a next frame in a buffer associated with the second pipeline;   determine the second timecode is less than the first timecode; and   decrease the size of the buffer based at least on a difference between the second timecode and the first timecode.   
     
     
         17 . The system of  claim 11 , wherein the instructions, when executed, further cause the system to:
 identify a first timecode associated with a last frame sent to the output pipeline from the first pipeline;   identify a second timecode associated with a next frame in a buffer associated with the second pipeline;   determine the second timecode is equal to the first timecode; and   maintain the size of the buffer.   
     
     
         18 . The system of  claim 11 , wherein the output pipeline comprises an output buffer having a size based at least on an output bitrate and a time to switch from the output of the first pipeline and the output of the second pipeline. 
     
     
         19 . An apparatus comprising:
 a first pipeline configured to receive a first bitstream;   a second pipeline configured to receive a second bitstream;   an output pipeline configured to receive an output from either of the first pipeline or the second pipeline; and   at least one processor configured to:
 determine an error has occurred in the first pipeline; and 
 send an output of the second pipeline to the output pipeline. 
   
     
     
         20 . The apparatus of  claim 19 , wherein the processor is further configured to:
 adjust a first size of a first buffer of the first pipeline and a second size of a second buffer of the second pipeline based at least on timing information associated with the first bitstream and the second bitstream.