Via etch method for back contact multijunction solar cells

Abstract

This disclosure relates to semiconductor devices and methods for fabricating semiconductor devices. Particularly, the disclosure relates to back-contact-only multijunction solar cells and the process flows for making such solar cells, including a wet etch process that removes semiconductor materials non-selectively without major differences in etch rates between heteroepitaxial III-V semiconductor layers.

What is claimed is: 
     
         1 . A through wafer via structure, comprising:
 a substrate having a front substrate surface and a back substrate surface;   a plurality of heteroepitaxial layers overlying the front substrate surface, wherein the plurality of heteroepitaxial layers comprises a top heteroepitaxial surface;   a first antireflection coating overlying a first portion of the plurality of heteroepitaxial layer;   a patterned cap region overlying a second portion of the plurality of heteroepitaxial layers and electrically connected to the plurality of heteroepitaxial layers;   a through-wafer-via disposed within the patterned cap region and extending from top heteroepitaxial surface to the back substrate surface, wherein the through-wafer-via comprises a sidewall;   a second antireflection coating overlying a third portion of the plurality of heteroepitaxial layers and overlying the sidewall of the through-wafer-via;   a front side metal overlying the patterned cap region and the second antireflection coating;   an optical adhesive overlying the first antireflection coating, the patterned cap region, the front side metal; and   a coverglass overlying the optical adhesive.   
     
     
         2 . The through-wafer via structure of  claim 1 , comprising a metal plug overlying the second antireflection coating within the through-wafer-via, and wherein the optical adhesive overlies the metal gold plug. 
     
     
         3 . The through-wafer via structure of  claim 1 , comprising a gold plug overlying the second antireflection coating within the through-wafer-via, and wherein the optical adhesive overlies the metal plug. 
     
     
         4 . The through-wafer via structure of  claim 1 , comprising:
 a passivation liner underlying a first portion of the back substrate surface and contacting the second antireflection coating;   a front surface metal pad underlying the passivation liner and electrically connected to the front side metal; and   a back side metal underlying a second portion of the back substrate surface.   
     
     
         5 . The through-wafer via structure of  claim 1 , wherein the substrate is less than 150 μm thick. 
     
     
         6 . The through-wafer via structure of  claim 1 , wherein the plurality of heteroepitaxial layers comprises at least two junctions of a multijunction solar cell. 
     
     
         7 . A semiconductor device comprising a plurality of the through-wafer-via structures of  claim 1 . 
     
     
         8 . The semiconductor device of  claim 7 , wherein the semiconductor device comprises a surface mount device. 
     
     
         9 . The semiconductor device of  claim 7 , wherein the semiconductor device is characterized by a unit mass per area of less than 0.09 g/cm 2 . 
     
     
         10 . The semiconductor device of  claim 7 , wherein the semiconductor device comprises a multijunction photovoltaic cell. 
     
     
         11 . A photovoltaic module comprising a plurality of the surface mount multijunction photovoltaic cells of  claim 10 . 
     
     
         12 . The photovoltaic module of  claim 10 , wherein the photovoltaic module comprises:
 a front surface area; and   the plurality of surface mount multijunction photovoltaic cells cover at least 70% of the front surface area.   
     
     
         13 . A power system comprising at least one photovoltaic module of  claim 10 . 
     
     
         14 . A method of fabricating a through-wafer-via structure, comprising:
 providing a semiconductor wafer, wherein the semiconductor wafer comprises:
 a substrate having a front substrate surface and a back substrate surface; 
 a plurality of heteroepitaxial layers overlying the front substrate surface; 
 an antireflection coating overlying a first portion of the plurality of heteroepitaxial layers; 
 a patterned cap region overlying a second portion of the plurality of heteroepitaxial layers and electrically connected to the plurality of heteroepitaxial layers; 
 a via extending from the plurality of heteroepitaxial layers to within the substrate, wherein the via comprises a sidewall; 
 the antireflection coating overlying a third portion of the plurality of heteroepitaxial layers and the via sidewall; 
 a front side metal overlying the patterned cap region and the antireflection coating overlying the third portion of the plurality of heteroepitaxial layers and the via sidewall; and 
 an optical adhesive overlying the antireflection coating, the patterned cap region, and the front side metal; 
 a coverglass overlying the optical adhesive; and 
   thinning the substrate to expose the front side metal at the bottom of the via.   
     
     
         15 . A method of fabricating a through wafer via structure, comprising:
 providing a semiconductor wafer, wherein the semiconductor wafer comprises:
 a substrate having a front substrate surface and a back substrate surface; 
 a plurality of heteroepitaxial layers overlying the front substrate surface; and 
 a cap layer overlying a first portion of the plurality of heteroepitaxial layer; 
   etching a via extending from the cap layer to within the substrate, wherein the via comprises a sidewall;   etching the cap layer to provide a patterned cap region overlying a first portion of the plurality of heteroepitaxial layers;   depositing an antireflection coating overlying a second portion of the plurality of heteroepitaxial layers, overlying a third portion of the plurality of heteroepitaxial layers, overlying the sidewall of the through-wafer-via, and overlying the substrate at the bottom of the via;   etching the antireflection coating on the bottom of the via to expose the substrate;   depositing a front surface contact overlying at least a portion of the patterned cap region, overlying a third portion of the plurality of heteroepitaxial layers, the sidewall of the via, and the bottom of the via;   applying an optical adhesive overlying the front surface contact, the patterned cap region, and the antireflection coating;   applying a coverglass overlying the optical adhesive; and   thinning the substrate to expose the front surface contact at the bottom of the via.   
     
     
         16 . The method of  claim 15 , wherein after the depositing the front surface contact, depositing a metal plug within the via. 
     
     
         17 . The method of  claim 15 , comprising:
 depositing a passivation liner underlying a first portion of the back substrate surface and contacting the antireflection coating on the via sidewall;   depositing front surface metal pad underlying the passivation liner and electrically connected to the front surface metal; and   depositing a back side metal on a second portion of the back substrate surface.   
     
     
         18 . The method of  claim 15 , wherein the plurality of heteroepitaxial layers comprises at least two junctions of a multijunction solar cell. 
     
     
         19 . The method of  claim 15 , wherein etching a via comprises wet etching using an etchant mixture comprising iodic acid, hydrofluoric acid, and water. 
     
     
         20 . The method of  claim 15 , wherein thinning the substrate comprises exposing the front surface contact at the bottom of the via. 
     
     
         21 . The method of  claim 15 , wherein thinning the substrate comprises wet etching, back-grinding, lift-off, or any combination of any of the foregoing. 
     
     
         22 . A semiconductor device comprising a through-wafer-via structure fabricated by the method of  claim 15 . 
     
     
         23 . The semiconductor device of  claim 22 , wherein the semiconductor device comprises a surface mount device. 
     
     
         24 . The semiconductor device of  claim 22 , wherein the semiconductor device comprises a multijunction photovoltaic cell. 
     
     
         25 . A photovoltaic module comprising a plurality of the semiconductor devices of  claim 24 . 
     
     
         26 . The photovoltaic module of  claim 25 , wherein the photovoltaic module comprises:
 a front surface area; and   the plurality of surface mount multijunction photovoltaic cells cover at least 70% of the front surface area.   
     
     
         27 . A power system comprising at least one photovoltaic module of  claim 25 .