Cortical processing with thermodynamic ram

Abstract

A thermodynamic RAM apparatus includes a physical substrate of addressable adaptive synapses that are temporarily partitioned to emulate adaptive neurons of arbitrary sizes, wherein the physical substrate mates electronically with a digital computing platform for high-throughput and low-power neuromorphic adaptive learning applications. The physical substrate addressable adaptive synapses can be configured as a part of a memristor-based physical neural processing unit.

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         8 . A thermodynamic RAM apparatus, comprising:
 a plurality of thermodynamic cores; and   a plurality of common read out electrodes, wherein each thermodynamic core among said plurality of thermodynamic cores comprises a physical substrate comprising at least one memristor that is selectively coupled to said at least one common read-out electrode among said plurality of common read-out electrodes, and wherein said physical substrate provides a synaptic integration and a learning resource for a digital computing platform.   
     
     
         9 . The apparatus of  claim 8  wherein said at least one memristor comprises an addressable adaptive synapse. 
     
     
         10 . The apparatus of  claim 8  wherein said digital computing platform comprises a CPU (Central Processing Unit) that communicates electronically with said plurality of thermodynamic cores. 
     
     
         11 . The apparatus of  claim 8  wherein said digital computing platform includes at least one PCI bus that communicates electronically with said plurality of thermodynamic cores. 
     
     
         12 . The apparatus of  claim 8  wherein said digital computing platform includes at least one LPC bus that communicates electronically with said plurality of thermodynamic cores. 
     
     
         13 . The apparatus of  claim 8  wherein said digital computing platform includes at least one North Bridge that communicates electronically with said plurality of thermodynamic cores. 
     
     
         14 . The thermodynamic RAM apparatus of  claim 8  wherein said each thermodynamic core is emulated with digital electronics. 
     
     
         15 . A thermodynamic RAM apparatus, comprising:
 a plurality of thermodynamic cores; and   a plurality of common read out electrodes, wherein each thermodynamic core among said plurality of thermodynamic cores comprises a physical substrate comprising at least one transistor that is selectively coupled to said at least one common read-out electrode among said plurality of common read-out electrodes, and wherein said physical substrate provides a synaptic integration and a learning resource for a digital computing platform.   
     
     
         16 . The apparatus of  claim 15  further comprising an addressable adaptive synapse that comprises said at least one transistor. 
     
     
         17 . The apparatus of  claim 15  herein said digital computing platform comprises a CPU (Central Processing Unit) that communicates electronically with said, plurality of thermodynamic cores. 
     
     
         18 . The apparatus of  claim 15  wherein said digital computing platform includes at least one PCI bus that communicates electronically with said plurality of thermodynamic cores. 
     
     
         19 . The apparatus of  claim 15  wherein said digital computing platform includes at least one LPC bus that communicates electronically with said plurality of thermodynamic cores. 
     
     
         20 . The apparatus of  claim 15  wherein said digital computing, platform includes at least one North Bridge that communicates electronically with said plurality of thermodynamic cores. 
     
     
         21 . The thermodynamic RAM apparatus of  claim 15  wherein said each thermodynamic core is emulated with digital electronics. 
     
     
         22 . The thermodynamic RAM apparatus of  claim 23  wherein said addressable adaptive synapse is configured as a part of a memristor-based physical neural processing unit. 
     
     
         23 . A thermodynamic RAM apparatus, comprising:
 a plurality of thermodynamic cores; and   a plurality of common read out electrodes, wherein each thermodynamic core among said plurality of thermodynamic cores comprises a physical substrate comprising an addressable adaptive synapse comprising at least one memristor and/or at least one transistor that is selectively coupled to said at least one common read-out electrode among said plurality of common read-out electrodes, and wherein said physical substrate provides a synaptic integration and a learning resource for a digital computing platform.