Method for fabricating conducting structure and thin film transistor array panel

Abstract

A method of providing a conducting structure over a substrate, which comprises: disposing a lower sub-layer over a substrate, the lower sub-layer comprising a conductive metal oxide material that includes indium and zinc, wherein the indium and zinc content in the bottom sub-layer substantially defines a first indium to zinc content ratio; performing a first hydrogen treatment over an exposed surface of the lower sub-layer for introducing hydrogen content therein; disposing a middle sub-layer over the lower sub-layer, the middle sub-layer comprising a metal material; disposing an upper sub-layer over the middle sub-layer, the upper sub-layer comprising a conductive metal oxide material that includes indium and zinc, wherein the indium and the zinc content in the upper sub-layer substantially defines a second indium to zinc content ratio smaller than the first indium to zinc content ratio; and patterning the multi-layered conductive structure to generate a composite lateral etch profile.

1 - 21 . (canceled) 
     
     
         22 . A thin film transistor array panel, comprising:
 a substrate;   a first conductive layer on the substrate and comprising a gate electrode;   a channel layer on the gate electrode and insulated there-from; and   a second conductive layer on the channel layer, the second conductive layer comprising a multi-layered portion defining a source electrode and a drain electrode, wherein the multi-layered portion of the second conductive layer comprises:
 a first sub-layer on the channel layer and in electrical contact with the channel layer, 
 a second sub-layer on the first sub-layer, and 
 a third sub-layer on the second sub-layer;
 wherein each of the third sub-layer and the first sub-layer comprises a metal oxide material containing hydrogen; 
 wherein a gap is in the second conductive layer and between the source electrode and the drain electrode; the gap extends through the first sub-layer, the second sub-layer, and the third sub-layer; and 
 wherein a gap width in the third sub-layer is wider than a gap width in the first sub-layer. 
 
   
     
     
         23 . The thin film transistor array panel of  claim 22 , wherein each of the third sub-layer and the first sub-layer comprises the metal oxide material containing indium and zinc. 
     
     
         24 . The thin film transistor array panel of  claim 23 , wherein an indium-to-zinc content ratio in the first sub-layer is greater than an indium-to-zinc content ratio in the third sub-layer. 
     
     
         25 . The thin film transistor array panel of  claim 24 , wherein the indium-to-zinc content ratio difference between the first sub-layer and the third sub-layer is not less than 20%. 
     
     
         26 . The thin film transistor array panel of  claim 25 , wherein the indium-to-zinc content ratio in the first sub-layer is in a range from about 25% to about 80%. 
     
     
         27 . The thin film transistor array panel of  claim 26 , wherein the indium-to-zinc content ratio in the first sub-layer is in a range from about 45% to about 70%. 
     
     
         28 . The thin film transistor array panel of  claim 25 , wherein the indium-to-zinc content ratio in the third sub-layer is in a range from about 5% to about 40%. 
     
     
         29 . The thin film transistor array panel of  claim 28 , wherein the indium-to-zinc content ratio in the third sub-layer is a in range from about 10% to about 35%. 
     
     
         30 . The thin film transistor array panel of  claim 24 , wherein the indium-to-zinc content ratio differentiation between the first sub-layer and the third sub-layer affects a generation of a substantially smooth and tapered lateral profile for the gap defined between the source electrode and the drain electrode. 
     
     
         31 . The thin film transistor array panel of  claim 30 , wherein the lateral profile associated with the gap corresponds to a taper angle of about 40 degrees to 85 degrees with respect to a surface defined by the substrate. 
     
     
         32 . A method of providing a thin film transistor array panel, comprising:
 forming a channel material layer over a substrate, the channel material layer comprising an oxide semiconductor material;   forming a lower sub-layer over a substrate, the lower sub-layer comprising a conductive metal oxide material that includes indium and zinc, wherein the indium and zinc content in the bottom sub-layer substantially defines a first indium-to-zinc content ratio;   forming a middle sub-layer over the lower sub-layer, the middle sub-layer comprising a metal material;   forming an upper sub-layer over the middle sub-layer, the upper sub-layer comprising a conductive metal oxide material that includes indium and zinc, wherein the indium and the zinc content in the upper sub-layer substantially defines a second indium-to-zinc content ratio smaller than the first indium-to-zinc content ratio; and   patterning the lower sub-layer, the middle sub-layer, and upper sub-layer to form a gap extending through the lower sub-layer, the middle sub-layer, and upper sub-layer.   
     
     
         33 . The method of  claim 32 , wherein the indium-to-zinc content ratio difference between the first sub-layer and the third sub-layer is not less than 20%. 
     
     
         34 . The method of  claim 32 , wherein patterning the lower sub-layer, the middle sub-layer, and upper sub-layer comprises defining a source electrode and a drain electrode of a semiconductor device, wherein the indium-to-zinc content ratio differentiation between the lower sub-layer and the upper sub-layer affects a generation of a substantially smooth and tapered lateral etch profile between the source electrode and the drain electrode. 
     
     
         35 . A method of providing a thin film transistor array panel, comprising:
 forming a channel material layer over a substrate, the channel material layer comprising an oxide semiconductor material;   forming a lower sub-layer over a substrate, the lower sub-layer comprising a conductive metal oxide material that includes indium and zinc, wherein the indium and zinc content in the bottom sub-layer substantially defines a first indium-to-zinc content ratio;   forming a middle sub-layer over the lower sub-layer, wherein the middle sub-layer is made of copper or copper alloy;   forming an upper sub-layer over the middle sub-layer, the upper sub-layer comprising a conductive metal oxide material that includes indium and zinc, wherein the indium and the zinc content in the upper sub-layer substantially defines a second indium-to-zinc content ratio smaller than the first indium-to-zinc content ratio; and   patterning the lower sub-layer, the middle sub-layer, and upper sub-layer to form a gap extending through the lower sub-layer, the middle sub-layer, and upper sub-layer.   
     
     
         36 . The method of  claim 35 , wherein the indium-to-zinc content ratio difference between the first sub-layer and the third sub-layer is not less than 20%. 
     
     
         37 . The method of  claim 35 , wherein patterning the lower sub-layer, the middle sub-layer, and upper sub-layer comprises defining a source electrode and a drain electrode of a semiconductor device, wherein the indium-to-zinc content ratio differentiation between the lower sub-layer and the upper sub-layer affects a generation of a substantially smooth and tapered lateral etch profile between the source electrode and the drain electrode.