Technologies for managing a flexible host interface of a network interface controller

Abstract

Technologies for processing network packets by a host interface of a network interface controller (NIC) of a compute device. The host interface is configured to retrieve, by a symmetric multi-purpose (SMP) array of the host interface, a message from a message queue of the host interface and process, by a processor core of a plurality of processor cores of the SMP array, the message to identify a long-latency operation to be performed on at least a portion of a network packet associated with the message. The host interface is further configured to generate another message which includes an indication of the identified long-latency operation and a next step to be performed upon completion. Additionally, the host interface is configured to transmit the other message to a corresponding hardware unit scheduler as a function of the subsequent long-latency operation to be performed. Other embodiments are described herein.

1 . A compute device for processing network packets, the compute device comprising:
 a compute engine having one or more processors and a memory; and   a network interface controller (NIC) having a host interface, wherein the NIC is to:
 retrieve, by a symmetric multi-purpose (SMP) array of the host interface, a message from a message queue of the host interface; 
 process, by a processor core of a plurality of processor cores of the SMP array, the message to identify a long-latency operation to be performed on at least a portion of a network packet associated with the message; 
 generate, by the processor core and in response to having identified the long-latency operation to be performed, another message which includes an indication of the long-latency operation to be performed and a next step to be performed upon completion of the long-latency operation; and 
 transmit, by the processor core, the other message to a corresponding hardware unit scheduler of the host interface as a function of the long-latency operation to be performed. 
   
     
     
         2 . The compute device of  claim 1 , wherein the NIC is further to:
 generate, by the processor core and in response to having identified that no long-latency operations are to be performed based on the processing of the message, a release message which indicates the network packet can be released to one of the one or more processors or a network interface of the NIC; and   transmit, by the processor core, the release message to a memory fabric interface of a memory fabric of the NIC.   
     
     
         3 . The compute device of  claim 1 , wherein the NIC is further to:
 retrieve, by a job manager of the host interface, an index of a descriptor in a descriptor table stored by a processor of the one or more processors at a location in the memory, wherein the descriptor includes information corresponding to a network packet;   forward, by the job manager, a first message to the symmetric multi-purpose (SMP) array of the host interface, wherein the first message includes the index of the descriptor;   process, by a first processor core of the plurality of processor cores of the SMP array, the first message to identify the index of the descriptor;   generate, by the first processor core, a second message that indicates to perform a fetch operation to retrieve the descriptor based on the index of the descriptor and includes an indication that the retrieved descriptor is to be processed upon retrieval; and   forward, by the first processor core, the second message to a direct memory access (DMA) engine of the host interface.   
     
     
         4 . The compute device of  claim 3 , wherein the NIC is further to:
 process, by the DMA engine, the second message to identify a DMA fetch operation to be performed, wherein the DMA fetch operation to be performed comprises to fetch the descriptor via DMA;   perform, by the DMA engine, the identified DMA fetch operation;   generate, by the DMA engine, a third message which includes the descriptor retrieved as a result of the DMA fetch operation, wherein the third message includes a location of the descriptor in a buffer memory of the host interface and the indication that the retrieved descriptor is to be processed; and   forward, by the DMA engine, the third message to the SMP array.   
     
     
         5 . The compute device of  claim 3 , wherein to forward the first message to the SMP array comprises to enqueue the message in a descriptor queue accessible by the SMP array. 
     
     
         6 . The compute device of  claim 3 , wherein to retrieve the index of the descriptor comprises to retrieve the index of the descriptor from a descriptor ring stored in a cache memory of the compute engine. 
     
     
         7 . The compute device of  claim 6 , wherein the NIC is further to:
 receive, by the job manager, an authorized traffic limit from a traffic manager of the NIC, wherein the authorized traffic limit indicates an amount of network traffic the job manager is allowed to process upon receipt;   retrieve, by the job manager, a next descriptor from the descriptor table;   interpret, by the job manager, the next descriptor to determine the amount of network traffic associated with the next descriptor;   determine, by the job manager, whether the authorized traffic limit would be exceeded if the network traffic associated with the next descriptor were to be processed as a function of the amount of network traffic associated with the next descriptor and the authorized traffic limit; and   return, by the job manager and subsequent to having determined that the authorized traffic limit would be exceeded, the descriptor to the descriptor table.   
     
     
         8 . The compute device of  claim 7 , wherein the NIC is further to:
 decrease, by the job manager and subsequent to having determined that the authorized traffic limit would not be exceeded, the authorized traffic limit by the amount of network traffic associated with the next descriptor;   generate, by the job manager, a fourth message that includes information usable to locate the descriptor; and   insert, by the job manager, the message into a descriptor queue accessible by the SMP array.   
     
     
         9 . The compute device of  claim 1 , wherein to identify the long-latency operation comprises to identify a direct memory access (DMA) fetch operation. 
     
     
         10 . The compute device of  claim 1 , wherein the NIC is further to:
 receive, by an event logic unit of the host interface, an event notification; and   build, by the event logic unit, a data structure as a function of a network protocol associated with the event notification, wherein the data structure includes information about the event notification usable by at least one of the plurality of processor cores of the SMP array to process the event notification.   
     
     
         11 . The compute device of  claim 10 , wherein to receive the event notification comprises to receive the event notification which indicates one of a signaling event, a memory-mapped input/output event, or a host fabric interface event. 
     
     
         12 . One or more machine-readable storage media comprising a plurality of instructions stored thereon that, in response to being executed, cause a compute device to:
 retrieve, by a symmetric multi-purpose (SMP) array of a host interface of a network interface controller (NIC) of the compute device, a message from a message queue of the host interface;   process, by a processor core of a plurality of processor cores of the SMP array, the message to identify a long-latency operation to be performed on at least a portion of a network packet associated with the message;   generate, by the processor core and in response to having identified the long-latency operation to be performed, another message which includes an indication of the long-latency operation to be performed and a next step to be performed upon completion of the long-latency operation; and   transmit, by the processor core, the other message to a corresponding hardware unit scheduler of the host interface as a function of the long-latency operation to be performed.   
     
     
         13 . The one or more machine-readable storage media of  claim 12 , wherein the plurality of instructions further cause the compute device to:
 generate, by the processor core and in response to having identified that no long-latency operations are to be performed based on the processing of the message, a release message which indicates the network packet can be released to one of the one or more processors or a network interface of the NIC; and   transmit, by the processor core, the release message to a memory fabric interface of a memory fabric of the NIC.   
     
     
         14 . The one or more machine-readable storage media of  claim 12 , wherein the plurality of instructions further cause the compute device to:
 retrieve, by a job manager of the host interface, an index of a descriptor in a descriptor table stored by a processor of the one or more processors at a location in the memory, wherein the descriptor includes information corresponding to a network packet;   forward, by the job manager, a first message to the symmetric multi-purpose (SMP) array of the host interface, wherein the first message includes the index of the descriptor;   process, by a first processor core of the plurality of processor cores of the SMP array, the first message to identify the index of the descriptor;   generate, by the first processor core, a second message that indicates to perform a fetch operation to retrieve the descriptor based on the index of the descriptor and includes an indication that the retrieved descriptor is to be processed upon retrieval; and   forward, by the first processor core, the second message to a direct memory access (DMA) engine of the host interface.   
     
     
         15 . The one or more machine-readable storage media of  claim 14 , wherein the plurality of instructions further cause the compute device to:
 process, by the DMA engine, the second message to identify a DMA fetch operation to be performed, wherein the DMA fetch operation to be performed comprises to fetch the descriptor via DMA;   perform, by the DMA engine, the identified DMA fetch operation;   generate, by the DMA engine, a third message which includes the descriptor retrieved as a result of the DMA fetch operation, wherein the third message includes a location of the descriptor in a buffer memory of the host interface and the indication that the retrieved descriptor is to be processed; and   forward, by the DMA engine, the third message to the SMP array.   
     
     
         16 . The one or more machine-readable storage media of  claim 14 , wherein to forward the first message to the SMP array comprises to enqueue the message in a descriptor queue accessible by the SMP array. 
     
     
         17 . The one or more machine-readable storage media of  claim 14 , wherein to retrieve the index of the descriptor comprises to retrieve the index of the descriptor from a descriptor ring stored in a cache memory of the compute engine. 
     
     
         18 . The one or more machine-readable storage media of  claim 17 , wherein the plurality of instructions further cause the compute device to:
 receive, by the job manager, an authorized traffic limit from a traffic manager of the NIC, wherein the authorized traffic limit indicates an amount of network traffic the job manager is allowed to process upon receipt;   retrieve, by the job manager, a next descriptor from the descriptor table;   interpret, by the job manager, the next descriptor to determine the amount of network traffic associated with the next descriptor;   determine, by the job manager, whether the authorized traffic limit would be exceeded if the network traffic associated with the next descriptor were to be processed as a function of the amount of network traffic associated with the next descriptor and the authorized traffic limit; and   return, by the job manager and subsequent to having determined that the authorized traffic limit would be exceeded, the descriptor to the descriptor table.   
     
     
         19 . The one or more machine-readable storage media of  claim 18 , wherein the plurality of instructions further cause the compute device to:
 decrease, by the job manager and subsequent to having determined that the authorized traffic limit would not be exceeded, the authorized traffic limit by the amount of network traffic associated with the next descriptor;   generate, by the job manager, a fourth message that includes information usable to locate the descriptor; and   insert, by the job manager, the message into a descriptor queue accessible by the SMP array.   
     
     
         20 . The one or more machine-readable storage media of  claim 12 , wherein the plurality of instructions further cause the compute device to:
 receive, by an event logic unit of the host interface, an event notification; and   build, by the event logic unit, a data structure as a function of a network protocol associated with the event notification, wherein the data structure includes information about the event notification usable by at least one of the plurality of processor cores of the SMP array to process the event notification.   
     
     
         21 . The one or more machine-readable storage media of  claim 21 , wherein to receive the event notification comprises to receive the event notification which indicates one of a signaling event, a memory-mapped input/output event, or a host fabric interface event. 
     
     
         22 . A compute device for processing network packets, the compute device comprising:
 means for retrieving, by a symmetric multi-purpose (SMP) array of a host interface of a network interface controller (NIC) of the compute device, a message from a message queue of the host interface;   means for processing, by a processor core of a plurality of processor cores of the SMP array, the message to identify a long-latency operation to be performed on at least a portion of a network packet associated with the message;   means for generating, by the processor core and in response to having identified the long-latency operation to be performed, another message which includes an indication of the long-latency operation to be performed and a next step to be performed upon completion of the long-latency operation; and   means for transmitting, by the processor core, the other message to a corresponding hardware unit scheduler of the host interface as a function of the long-latency operation to be performed.   
     
     
         23 . The compute device of  claim 22 , further comprising:
 means for generating, by the processor core and in response to having identified that no long-latency operations are to be performed based on the processing of the message, a release message which indicates the network packet can be released to one of one or more processors of a compute engine of the compute device or a network interface of the NIC; and   means for transmitting, by the processor core, the release message to a memory fabric interface of a memory fabric of the NIC.   
     
     
         24 . The compute device of  claim 22 , further comprising:
 means for retrieving, by a job manager of the host interface, an index of a descriptor in a descriptor table stored by a processor of one or more processors of a compute engine of the compute device at a location in a memory of the compute engine, wherein the descriptor includes information corresponding to a network packet;   means for forwarding, by the job manager, a first message to the symmetric multi-purpose (SMP) array of the host interface, wherein the first message includes the index of the descriptor;   means for processing, by a first processor core of the plurality of processor cores of the SMP array, the first message to identify the index of the descriptor;   means for generating, by the first processor core, a second message that indicates to perform a fetch operation to retrieve the descriptor based on the index of the descriptor and includes an indication that the retrieved descriptor is to be processed upon retrieval; and   means for forwarding, by the first processor core, the second message to a direct memory access (DMA) engine of the host interface.   
     
     
         25 . The compute device of  claim 24 , further comprising:
 means for processing, by the DMA engine, the second message to identify a DMA fetch operation to be performed, wherein the DMA fetch operation to be performed comprises to fetch the descriptor via DMA;   means for performing, by the DMA engine, the identified DMA fetch operation;   means for generating, by the DMA engine, a third message which includes the descriptor retrieved as a result of the DMA fetch operation, wherein the third message includes a location of the descriptor in a buffer memory of the host interface and the indication that the retrieved descriptor is to be processed; and   means for forwarding, by the DMA engine, the third message to the SMP array.