Trace anywhere interconnect

Abstract

The present invention provides for a method and structure for forming three-dimensionally routed dielectric wires between discrete points on the two or more parallel circuit planes. The wires may be freely routed in three-dimensional space as to create the most efficient routing between the two arbitrarily defined points on the two or more parallel circuit planes. Metalizing the outer surfaces of these three dimensional dielectric wires electrically coupling the discrete wires to their respective discrete contact points. Two or more of these wires may be in intimate contact to one another electrically coupling to each other as well as to two or more discrete contact pads. These electrically coupled contact pads may be on opposite sides or on the same side of the structure and the formed metalized wires may originate on one side and terminate on the other or originate and terminate from the same side.

What is claimed: 
     
         1 . A method for fabricating an interconnect mechanism or device comprising the steps of:
 providing a flat carrier of glass, ceramic or some other smooth, flat material such as but not limited to s smooth metallic block;   temporarily bonding a sheet of metallic foil preferably Cu to the flat material carrier to keep the Cu flat with a suitable bonding material such as but not limited to adhesive or wax. Said sheet of foil having a foil thickness in a range but not limited to 10 um to 35 um;   forming on top of the Cu foils dielectric wires attached to the Cu foil grow-up from predetermined locations on the foil to predetermined location in free space in the z axis by utilizing commercially known 3d printing techniques;   treating said foil to promote adhesion of the dielectric wires through micro-etching plasma or other surface treatment; said wires are in a range of 1 um to 50 um in diameter and are built up to a z-axis height approximately 25 um to 100 um above an overall height of the planned interconnect mechanism in a range of from 100 um to 0.200 thick;   metalizing the free formed wires extending from the Cu sheet with one of either electro-plating, electro-less plating, Chemical vapor deposition, sputter coating or any other technique known in the art, said thickness of this metallization will typically be in the range of 1 um to 20 um; said metallization coating the dielectric wires as well as the exposed surface area of the base foil making the base foil and the coated wires electrically coupled.   
     
     
         2 . The method for fabricating an interconnect mechanism or device according to  claim 1  wherein the metalized dielectric wires are be coated again with a dielectric. 
     
     
         3 . The method according to  claim 2  wherein said coating with said dielectric is done via a dip operation, silicon Chemical Vapor deposition (SCVD) Silica Pulsed layer Deposition (PLD), Titania Atomic Layer Deposition (ALD) or other techniques known in the art. 
     
     
         4 . The method according to  claim 2  wherein during this process a top side, of the base foil metallization can be coated as well, electrically isolating it from further processes. 
     
     
         5 . The method according to  claim 2  wherein the coated wires are then metallized to short all the surfaces of the formed wires together. 
     
     
         6 . The method according to  claim 5  wherein tying this metallization to one or more ground wires or outer circuit layers t creates ground shielding for all wires as well as approximates coaxial wires for all signal wires. 
     
     
         7 . The method according to  claim 6  wherein coupling this ground metallization can be achieved through selective removal of the outer coating of dielectric, via laser ablation, or some other technique known in the art, from the wires or areas of the base copper designed to be ground when the interconnect ultimately couples two or more electronic devices. 
     
     
         8 . The method according to  claim 1  wherein the wires are then formed with or without a second dielectric and second metallization and the structure can be filled with a dielectric such as but not limited to epoxy via a molding operation) curing the epoxy into a rigid substrate. It would be best to over mold the epoxy beyond the top end points of the formed wires by approximately 25 um-100 um. thereby permitting enough material for a planarization process via grinding, sanding, lapping or other techniques know in the art. 
     
     
         9 . The method according to  claim 7  wherein the wires having a second dielectric and second metallization top tips of the wires may be coated with a temporary coating such as wax or a temporary polymer to prevent metallization from forming at the last 25 um to 100 um on a second dielectric layer. 
     
     
         10 . The method according to  claim 8  wherein planarization also reveals the tops of the metalized wires providing the opportto build up a second circuit layer while electrically coupling said circuit layer to the wires and the base foil so that if tips of the coated wires have been spared from secondary metallization then carefully controlling the planarization of the interconnect substrate in the z-axis will reveal the first metalized layer of the formed wire exposing it to be electrically coupled to the aforementioned second circuit plane formation without coupling the aforementioned optional second metallization of the formed wire to the second circuit plane layer. 
     
     
         11 . The method according to  claim 10  wherein said second circuit plane layer is then formed via electro-less plating, Chemical vapor deposition, sputter coating, electro-plating, or any other technique known in the art. 
     
     
         12 . The method according to  claim 1  wherein the conductive metallization is preferable Cu, Au or any other suitable conductive material and or multiple layers of different materials. 
     
     
         13 . The method according to  claim 10  wherein after lifting the inter-connect off the smooth substrate, a primary bottom metallic layer, and a secondary top layer is formed into discreet circuitry through a traditional photo lithographic etching processes. 
     
     
         14 . The method according to  claim 13  wherein said contact points or pads are formed through this circuitization process are additionally plated with suitable metallic alloys for the desired application such as but not limited to wear resistance or solder-ability. 
     
     
         15 . The method according to  claim 1  wherein instead of a dielectric core in the wires, a metal core is substituted through use of negative 3D printing techniques utilizing but not limited to negative working photo sensitive epoxy whereby a temporary dielectric is formed through the entire active area of the interconnect except where the core wire metallization is to be formed. Then metallization is formed through electro-plating, electro-less plating, Chemical vapor deposition, sputter coating or other techniques known in the art to form a sold metallic wire structure. 
     
     
         16 . The method according to  claim 15  wherein varying metals of varying thicknesses are formed on inner walls of voided structures in epoxy layers providing the desirable electrical and mechanical properties for the interconnect mechanism, then temporary epoxy is removed through stripping techniques and freestanding metallic wires or tubes remain for continued processing. 
     
     
         17 . The method according to  claim 15  wherein dielectric cored, metallic cored or metallic tubes with or without additional layers of dielectric and metallization for shielding or coaxial vias could be formed on to discrete metallic pads or circuits pre-formed on to said smooth glass or smooth ceramic or other suitable material through electro-plating, electro-less plating, Chemical vapor deposition, sputter coating or any other technique known in the art 
     
     
         18 . The method according to  claim 17  wherein dimensions of said discrete metallic pads are defined through a temporary photo-lithographic process common in the art and the pads or the circuits are formed utilizing a laser stenciling process whereby a metallic foil is adhered temporarily to the smooth flat base material with an adhesive or wax for wire formation may be built on top of the discrete pads or circuitry. 
     
     
         19 . The method according to  claim 15  wherein the end points of the formed wires are discrete pads and or circuitry with varying geometric shapes formed based on an intended application of the inter-connect and solderable pads or pins of varying shapes for making contact to electrical terminals are formed and metalized 
     
     
         20 . The method according to  claim 19  wherein the formation and metallization of the end points of the formed wires in one step saves additional processing time and in combination with the formation of the discrete pads on the base metal layer and provides the opportunity for flush circuit pads on both ends on the inter-connect once the epoxy molding process in completed. 
     
     
         21 . The method according to  claim 1  wherein an elastomer or rubber compound potting material is substituted for a rigid potting compound providing the interconnect terminals with compliance for mating non-coplanar electronic device surfaces and by varying the durometer of the potting material as well as the formed wires material, thickness, length and shape the total amount of compliance, force and longevity of each of the formed wire mating terminals is controlled. 
     
     
         22 . The method according to  claim 1  wherein, in the event of a compliant interconnect a latticework, posts, or a solid block of a suitable hard material such as but not limited to epoxy is formed within the open spaces of the inter-connect not occupied by the formed wires or the compliant potting material. 
     
     
         23 . The method according to  claim 22  wherein said structures are formed through 3D printing techniques, in open spaces of the interconnect body, with a height slightly thinner than the overall thickness of the interconnect in a range of ˜10 um to 200 um providing the interconnect structure with a hard compression stop against the two mating surfaces of the devices intended to be electrically coupled thereby preventing over compression and damage of the interconnect structure.