Processor and method for outer product accumulate operations

Abstract

A processor and method for performing outer product and outer product accumulation operations on vector operands requiring large numbers of multiplies and accumulations is disclosed.

1 . (canceled) 
     
     
         2 . A system comprising:
 a memory storing a first plurality of multiplier operands and a second plurality of multiplicand operands;   a processor coupled to the memory to receive the first plurality of multiplier operands and the second plurality of multiplicand operands and to multiply each one of the first plurality of multiplier operands with every one of the second plurality of multiplicand operands, the processor including an array of circuit tiles arranged in rows and columns, each circuit tiles in the array including:
 a multiplier circuit coupled to receive one multiplier operand and one multiplicand operand and provide a multiplication result; 
 an adder circuit coupled to the multiplier circuit to receive the multiplication result, add it to any previous multiplication result stored in an accumulator circuit and provide a sum; and 
 the accumulator circuit coupled to the adder circuit to store the sum as an accumulation result. 
   
     
     
         3 . A system as in  claim 2  wherein:
 the array of circuit tiles has a same number n of rows and columns; 
 the processor includes a register file having a bit width of r bits; and 
 each one of a plurality of multiplier operands and each one of the plurality of multiplicand operands has a bit width of b bits, and an aggregate width of r bits where r=n*b. 
 
     
     
         4 . A system as in  claim 2  wherein the accumulator circuit stores more than one copy of the accumulation result. 
     
     
         5 . A system as in  claim 2  wherein each circuit tile in the array further includes an output stage circuit coupled to the accumulator circuit for storing the accumulation result before transfer of the accumulation result from the array. 
     
     
         6 . A system as in  claim 5  wherein each circuit tile in the array further includes a switching circuit coupled between the accumulator circuit and the output stage circuit for controlling data provided to the output stage circuit. 
     
     
         7 . A system as in  claim 6  wherein the switching circuit is also coupled to another accumulator circuit elsewhere in the array of circuit tiles having data to be provided to the output stage circuit. 
     
     
         8 . A system as in  claim 7  wherein each circuit tile in the array also includes a data processing circuit for performing further operations on data in the accumulator circuit, the data processing circuit coupled between the accumulator circuit and the output stage circuit. 
     
     
         9 . A system as in  claim 8  wherein the data processing circuit provides at least one of extraction of a portion of the data in the accumulator circuit, rounding of the data in the accumulator circuit, or application of a function to the data in the accumulator circuit. 
     
     
         10 . A system as in  claim 9  wherein the data processing circuit is coupled to at least two accumulator circuits. 
     
     
         11 . In a system for multiplying each one of a plurality of multiplier operands with every one of a plurality of multiplicand operands:
 a memory system for storing all of the multiplier operands and multiplicand operands;   a processor including a plurality of tiles, each tile including:
 a multiplier circuit coupled to receive one of the plurality of multiplier operands from the memory system and one of the plurality of multiplicand operands from the memory system and multiply them together to provide a multiplication result; 
 an adder circuit coupled to the multiplier circuit to receive the multiplication result and add it to a previous multiplication result to provide an addition result; and 
 an accumulator circuit coupled to the adder circuit to store the addition result. 
   
     
     
         12 . A tile as in  claim 11  further including an output stage circuit coupled to the accumulator circuit for storing the addition result. 
     
     
         13 . A tile as in  claim 12  further comprising a switching circuit coupled between the accumulator circuit and the output stage circuit for selecting data to be provided to the output stage circuit. 
     
     
         14 . A tile as in  claim 13  wherein the switching circuit enables data from another tile to be provided to the output stage circuit. 
     
     
         15 . In a system having a memory storing a vector multiplier and a vector multiplicand and a processor that includes an array of circuit tiles, each circuit tile in the array including a multiplier circuit, an adder circuit and an accumulator circuit, a method of performing an outer product accumulation of the vector multiplier and the vector multiplicand comprising:
 retrieving the vector multiplier and the vector multiplicand from the memory;   transmitting operands from the vector multiplier and operands from the vector multiplicand to each circuit tile in the array, the multiplier circuit at location [i, j] in the array receiving vector multiplier operand i and vector multiplicand operand j;   at each multiplier circuit in the array performing a multiplication of the vector multiplier operand and the vector multiplicand operand to produce a multiplication result;   providing the multiplication result to an adder circuit;   adding the multiplication result to a previous multiplication result stored in the accumulator circuit to provide a new accumulated result; and   storing the new accumulated result in the accumulator circuit.   
     
     
         16 . A method as in  claim 15  wherein a single instruction causes the processor to determine the outer product accumulation of the vector multiplier and the vector multiplicand. 
     
     
         17 . A method as in  claim 16  wherein each circuit tile in the array further includes an output stage circuit coupled to the accumulator circuit, and the method further comprises storing the new accumulation result in the output stage circuit. 
     
     
         18 . A method as in  claim 17  wherein each circuit tile in the array includes a switching circuit coupled between the accumulator circuit and the output stage circuit and coupled to another accumulator circuit the method further comprises operating the switching circuit to select data provided to the output stage circuit. 
     
     
         19 . A method as in  claim 18  wherein each circuit tile in the array includes a data processing circuit coupled to the accumulator circuit and the method further comprises using the data processing circuit to perform at least one of:
 extraction of a portion of data in the accumulator circuit; 
 rounding of data in the accumulator circuit; and 
 application of a function to data in the accumulator circuit.