Apparatus and Methods for Comparing Vectors

Abstract

Aspects for vector comparison in neural network are described herein. The aspects may include a direct memory access unit configured to receive a first vector and a second vector from a storage device. The first vector may include one or more first elements and the second vector may include one or more second elements. The aspects may further include a computation module that includes one or more comparers respectively configured to generate a comparison result by comparing one of the one or more first elements to a corresponding one of the one or more second elements in accordance with an instruction.

We claim: 
     
         1 . An apparatus for vector comparison in a neural network, comprising:
 a controller unit configured to receive a vector comparison instruction;   a direct memory access unit configured to receive a first vector and a second vector from a storage device, wherein the first vector includes one or more first elements and the second vector includes one or more second elements; and   a computation module that includes one or more comparers respectively configured to generate a comparison result by comparing one of the one or more first elements to a corresponding one of the one or more second elements in accordance with the vector comparison instruction.   
     
     
         2 . The apparatus of  claim 1 , wherein the vector comparison instruction includes a first address of the first vector, a second address of the second vector, and an output address for an output comparison vector. 
     
     
         3 . The apparatus of  claim 2 , wherein the vector comparison instruction further includes a bit length of the first vector and the second vector. 
     
     
         4 . The apparatus of  claim 3 , wherein the comparison result is generated as a true value based on a determination that the one of the one or more first elements is not less than the corresponding one of the one or more second elements if the vector comparison instruction is a greater-than-equal-to (GE) instruction. 
     
     
         5 . The apparatus of  claim 3 , wherein the comparison result is generated as a true value based on a determination that the one of the one or more first elements is not greater than the corresponding one of the one or more second elements if the vector comparison instruction is a less-than-equal-to (LE) instruction. 
     
     
         6 . The apparatus of  claim 3 , wherein the comparison result is generated as a true value based on a determination that the one of the one or more first elements is greater than the corresponding one of the one or more second elements if the vector comparison instruction is a greater-than (GT) instruction. 
     
     
         7 . The apparatus of  claim 3 , wherein the comparison result is generated as a true value based on a determination that the one of the one or more first elements is less than the corresponding one of the one or more second elements if the vector comparison instruction is a less-than (LT) instruction. 
     
     
         8 . The apparatus of  claim 3 , wherein the comparison result is generated as a true value based on a determination that the one of the one or more first elements is equal to the corresponding one of the one or more second elements if the vector comparison instruction is an equal-to (EQ) instruction. 
     
     
         9 . The apparatus of  claim 3 , wherein the comparison result is generated as a true value based on a determination that the one of the one or more first elements is not equal to the corresponding one of the one or more second elements if the vector comparison instruction is an unequal-to (UEQ) instruction. 
     
     
         10 . The apparatus of  claim 1 , wherein the computation module is further configured to combine the comparison results generated by the one or more comparers into an output comparison vector. 
     
     
         11 . The apparatus of  claim 1 , wherein the controller unit comprises an instruction obtaining module configured to obtain the vector comparison instruction from an instruction storage device. 
     
     
         12 . The apparatus of  claim 11 , wherein the controller unit further comprises a decoding module configured to decode the vector comparison instruction into one or more micro-instructions. 
     
     
         13 . The apparatus of  claim 12 , wherein the controller unit further comprises an instruction queue module configured to temporarily store the vector comparison instruction and one or more previously received instructions, and retrieve information corresponding to operation fields in the vector comparison instruction. 
     
     
         14 . The apparatus of  claim 13 , wherein the controller unit further comprises an instruction register configured to store the information corresponding to the operation fields in the vector comparison instruction. 
     
     
         15 . The apparatus of  claim 14 , wherein the controller unit further comprises a dependency processing unit configured to determine whether the vector comparison instruction has a dependency relationship with the one or more previously received instructions. 
     
     
         16 . The apparatus of  claim 15 , wherein the controller unit further comprises a storage queue module configured to store the vector comparison instruction while the dependency processing unit is determining whether the vector comparison instruction has the dependency relationship with the one or more previously received instructions. 
     
     
         17 . A method for vector comparison in a neural network, comprising:
 receiving, by a controller unit, a vector comparison instruction;   receiving, by a direct memory access unit, a first vector and a second vector from a storage device, wherein the first vector includes one or more first elements and the second vector includes one or more second elements; and   respectively generating, by one or more comparers of a computation module, a comparison result by comparing one of the one or more first elements to a corresponding one of the one or more second elements in accordance with the vector comparison instruction.   
     
     
         18 . The method of  claim 17 , wherein the vector comparison instruction includes a first address of the first vector, a second address of the second vector, and an output address for an output comparison vector. 
     
     
         19 . The method of  claim 18 , wherein the vector comparison instruction further includes a bit length of the first vector and the second vector. 
     
     
         20 . The method of  claim 19 , wherein the comparison result is generated as a true value based on a determination that the one of the one or more first elements is not less than the corresponding one of the one or more second elements if the instruction is a greater-than-equal-to (GE) instruction. 
     
     
         21 . The method of  claim 19 , wherein the comparison result is generated as a true value based on a determination that the one of the one or more first elements is not greater than the corresponding one of the one or more second elements if the instruction is a less-than-equal-to (LE) instruction. 
     
     
         22 . The method of  claim 19 , wherein the comparison result is generated as a true value based on a determination that the one of the one or more first elements is greater than the corresponding one of the one or more second elements if the instruction is a greater-than (GT) instruction. 
     
     
         23 . The method of  claim 19 , wherein the comparison result is generated as a true value based on a determination that the one of the one or more first elements is less than the corresponding one of the one or more second elements if the instruction is a less-than (LT) instruction. 
     
     
         24 . The method of  claim 19 , wherein the comparison result is generated as a true value based on a determination that the one of the one or more first elements is equal to the corresponding one of the one or more second elements if the instruction is an equal-to (EQ) instruction. 
     
     
         25 . The method of  claim 19 , wherein the comparison result is generated as a true value based on a determination that the one of the one or more first elements is not equal to the corresponding one of the one or more second elements if the instruction is an unequal-to (UEQ) instruction. 
     
     
         26 . The method of  claim 19 , further comprising combining, by the computation module, the comparison results generated by the one or more comparers into an output comparison vector. 
     
     
         27 . The method of  claim 26 , further comprising obtaining, by an instruction obtaining module of the controller unit, the vector comparison instruction from an instruction storage device. 
     
     
         28 . The method of  claim 27 , further comprising decoding, by a decoding module of the controller unit, the vector comparison instruction into one or more micro-instructions. 
     
     
         29 . The method of  claim 28 , further comprising temporarily storing, by an instruction queue module of the controller unit, the vector comparison instruction and one or more previously received instructions, and retrieve information corresponding to operation fields in the vector comparison instruction. 
     
     
         30 . The method of  claim 29 , further comprising storing, by an instruction register of the controller unit, the information corresponding to the operation fields in the vector comparison instruction. 
     
     
         31 . The method of  claim 30 , further comprising determining, by a dependency processing unit of the controller unit, whether the vector comparison has a dependency relationship with the one or more previously received instructions. 
     
     
         32 . The method of  claim 31 , further comprising storing, by a storage queue module of the controller unit, the vector comparison while the dependency processing unit is determining whether the vector comparison instruction has the dependency relationship with the one or more previously received instructions. 
     
     
         33 . An apparatus for vector comparison in a neural network, comprising:
 a controller unit configured to receive a vector comparison instruction;   a direct memory access unit configured to receive a first vector and a second vector from a storage device, wherein the first vector includes one or more first elements and the second vector includes one or more second elements; and   a computation module that includes one or more comparers respectively configured to generate a comparison result by comparing one of the one or more first elements to a corresponding one of the one or more second elements in accordance with the vector comparison instruction, wherein the vector comparison instruction includes a bit length of the first vector and the second vector.