Technologies for local disaggregation of memory

Abstract

Technologies for providing local disaggregation of memory include a compute sled. The compute sled includes a compute engine having a processor. The compute engine receives a request to perform a memory access operation on data residing in a first memory (e.g., a storage class memory) of the compute sled. The compute engine determines whether the data is cached in a second memory (e.g., a dynamic random-access memory (DRAM)). The compute engine performs, in response to a determination that the data is not cached in the second memory via a transactional protocol over a serial link connecting the processor and the first memory, the requested memory access operation.

1 . A compute sled, comprising:
 a compute engine comprising a processor, a first memory, and a second memory, wherein the compute engine is to (i) receive a request to perform a memory access operation on data residing in the first memory; (ii) determine whether the data is cached in the second memory; and (iii) perform, in response to a determination that the data is not cached in the second memory and via a transactional protocol over a serial link connecting the processor and the first memory, the requested memory access operation.   
     
     
         2 . The compute sled of  claim 1 , wherein the first memory is a storage class memory. 
     
     
         3 . The compute sled of  claim 2 , wherein the second memory is a dynamic random-access memory (DRAM). 
     
     
         4 . The compute sled of  claim 1 , wherein the first memory is to connected with the processor via one or more first memory channels. 
     
     
         5 . The compute sled of  claim 4 , wherein the second memory is connected with the processor via one or more second memory channels, each different from the first memory channels. 
     
     
         6 . The compute sled of  claim 1 , wherein the memory access operation is one of a read operation or a write operation. 
     
     
         7 . The compute sled of  claim 1 , wherein the compute engine is further to, perform, in response to a determination that the data is cached in the second memory, the requested memory access operation to the data at a memory address location in the second memory. 
     
     
         8 . The compute sled of  claim 7 , wherein to perform the requested memory access operation to the data at the memory address location in the second memory comprises to:
 determine the memory address location of the data in the second memory;   access the memory address location via a memory channel connecting the processor with the second memory; and   perform the memory access operation at the memory address location.   
     
     
         9 . The compute sled of  claim 1 , wherein to perform the requested memory access operation comprises to:
 determine a memory address location of the data in the first memory;   access the memory address location via a memory channel connecting the processor with the first memory; and   perform the memory access operation at the memory address location.   
     
     
         10 . The compute sled of  claim 1 , wherein the compute engine is further to return a response indicative of a completion of the performed memory access operation. 
     
     
         11 . The compute sled of  claim 1 , wherein the serial link is a PCIe (Peripheral Component Interconnect Express) link. 
     
     
         12 . The compute sled of  claim 1 , wherein the second memory is to cache a subset of the data residing in the first memory. 
     
     
         13 . One or more machine-readable storage media comprising a plurality of instructions stored thereon that, in response to being executed, cause a compute sled to:
 receive a request to perform a memory access operation on data residing in a first memory of the compute sled;   determine whether the data is cached in a second memory of the compute sled; and   perform, in response to a determination that the data is not cached in the second memory and via a transactional protocol over a serial link connecting a processor of the compute sled and the first memory, the requested memory access operation.   
     
     
         14 . The one or more machine-readable storage media of  claim 13 , wherein to receive the request to perform the memory access operation comprises to receive a request to perform a memory access operation on data residing in a storage class memory. 
     
     
         15 . The one or more machine-readable storage media of  claim 14 , wherein to determine whether the data is cached in the second memory of the compute sled comprises to determine whether the data is cached in a dynamic random-access memory (DRAM). 
     
     
         16 . The one or more machine-readable storage media of  claim 13 , wherein to determine whether the data is cached in the second memory of the compute sled further comprises to determine whether the data is cached in a second memory that is connected with the processor via one or more second memory channels different from a first memory channel that connects the first memory to the processor. 
     
     
         17 . The one or more machine-readable storage media of  claim 13 , wherein to receive the request to perform a memory access operation on the data comprises to receive a request to perform one of a read operation or a write operation on the data. 
     
     
         18 . The one or more machine-readable storage media of  claim 13 , wherein the plurality of instructions further cause the compute sled to perform, in response to a determination that the data is cached in the second memory, the requested memory access operation to the data at a memory address location in the second memory. 
     
     
         19 . The one or more machine-readable storage media of  claim 18 , wherein to perform the requested memory access operation to the data at the memory address location in the second memory comprises to:
 determine the memory address location of the data in the second memory;   access the memory address location via a memory channel connecting the processor with the second memory; and   perform the memory access operation at the memory address location.   
     
     
         20 . The one or more machine-readable storage media of  claim 13 , wherein to perform the requested memory access operation comprises to:
 determine a memory address location of the data in the first memory;   access the memory address location via a memory channel connecting the processor with the first memory; and   perform the memory access operation at the memory address location.   
     
     
         21 . The one or more machine-readable storage media of  claim 13 , wherein the plurality of instructions further cause the compute sled to return a response indicative of a completion of the performed memory access operation. 
     
     
         22 . The one or more machine-readable storage media of  claim 13 , wherein to perform the requested memory access operation comprises to perform the requested memory access operation via the transactional protocol over a PCIe (Peripheral Component Interconnect Express) link. 
     
     
         23 . The one or more machine-readable storage media of  claim 13 , wherein the plurality of instructions further cause the compute sled to cache, with the second memory, a subset of the data residing in the first memory. 
     
     
         24 . A compute sled comprising:
 circuitry for receiving a request to perform a memory access operation on data residing in a first memory of the compute sled;   means for determining whether the data is cached in a second memory of the compute sled; and   means for performing, in response to a determination that the data is not cached in the second memory and via a transactional protocol over a serial link connecting a processor of the compute sled and the first memory, the requested memory access operation.   
     
     
         25 . A method comprising:
 receiving, by a compute sled having a processor, a first memory, and a second memory, a request to perform a memory access operation on data residing in the first memory;   determining, by the compute sled, whether the data is cached in the second memory; and   performing, in response to a determination that the data is not cached in the second memory and via a transactional protocol over a serial link connecting the processor and the first memory, the requested memory access operation.   
     
     
         26 . The method of  claim 25 , further comprising performing, in response to a determination that the data is cached in the second memory, the requested memory access operation to the data at a memory address location in the second memory. 
     
     
         27 . The method of  claim 26 , wherein performing the requested memory access operation to the data at the memory address location in the second memory comprises:
 determining the memory address location of the data in the second memory;   accessing the memory address location via a memory channel connecting the processor with the second memory; and   performing the memory access operation at the memory address location.