US2019066256A1PendingUtilityA1

Specialized code paths in gpu processing

56
Assignee: INTEL CORPPriority: Dec 18, 2015Filed: Oct 25, 2018Published: Feb 28, 2019
Est. expiryDec 18, 2035(~9.4 yrs left)· nominal 20-yr term from priority
Inventors:Saurabh SharmaAbhishek VenkateshTravis T. SchluesslerThomas RaouxRahul P. SatheJon N. Hasselgren
G06F 8/41G06F 9/30149G06T 1/20G06T 15/005G06F 9/30145G06F 9/38G06F 9/3851G06F 9/35
56
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Claims

Abstract

Techniques to improve graphics processing unit (GPU) performance by introducing specialized code paths to process frequent common values are described. A shader compiler can determine instruction that, during operation, may output a common value and can introduce an enhanced shader instruction branch to process the common value to reduce overall computational requirements to execute the shader.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . An apparatus to compile a shader comprising:
 logic, at least a portion of which is implemented in hardware, the logic to:
 identify a shader instruction as an origin of a predetermined value based on analysis of the shader; and 
 compile the shader to include an enhanced sub-sequence to process an output of the predetermined value by the shader instruction, based on identification of the shader instruction as an origin of the predetermined value. 
   
     
     
         2 . The apparatus of  claim 1 , the logic to compile the shader omitting the enhanced sub-sequence. 
     
     
         3 . The apparatus of  claim 1 , the logic to:
 evaluate at least one coordinate; and   determine whether an output of the shader instruction is the predetermined value based on the at least one coordinate.   
     
     
         4 . The apparatus of  claim 1 , wherein the shader instruction comprises a sample_c instruction, a mul_sat instruction, an add_sat instruction, a ld instruction, a sample instruction, an AND instruction, a greater than instruction, an equal to instruction, or a less than instruction. 
     
     
         5 . The apparatus of  claim 4 , wherein the predetermined value comprises one or more common values, the common values comprising one, zero, 1.0f, 0.0f, or the like. 
     
     
         6 . The apparatus of  claim 1 , the logic to generate an enhanced shader based in part on compiling the shader instructions, the enhanced shader to:
 determine whether the output of the shader instruction equals the predetermined value; and   execute the enhanced sub-sequence based on a determination that the output of the shader instruction equals the predetermined value; or   execute a second sequence based on a determination that the output of the shader instruction does not equal the predetermined value, the second sequence requiring more graphics processing resources than the enhanced sub-sequence.   
     
     
         7 . The apparatus of  claim 1 , the logic to:
 determine whether the shader instruction can be folded based on identification of the shader instruction as an origin of the predetermined value; and   compile the shader to include the enhanced sub-sequence based on a determination that the shader instruction can be folded.   
     
     
         8 . The apparatus of  claim 7 , the logic to compile the shader omitting the enhanced sub-sequence based on a determination that the shader instruction cannot be folded. 
     
     
         9 . The apparatus of  claim 1 , the logic to:
 determine whether an output-merger (OM) state of the shader instruction is set to a src_alpha; and   compile the shader instruction to include the enhanced sub-sequence based on a determination that the OM state is set to src_alpha.   
     
     
         10 . The apparatus of  claim 9 , the logic to compile the shader instruction omitting the enhanced sub-sequence based on a determination that the OM state is not set to src_alpha. 
     
     
         11 . The apparatus of claim  claim 9 , the logic to:
 determine whether an alpha-max corresponding to the shader instruction is equal to zero; and   bind the shader based on a determination that the alpha_max corresponding to the shader instruction equals zero.   
     
     
         12 . The apparatus of  claim 1 , wherein the shader comprises a pixel shader, a vertex shader, a depth shader, a fragment shader, a domain shader, a hull shader, a computer shader, or a geometry shader. 
     
     
         13 . A computing-implemented method comprising:
 identifying a shader instruction as an origin of a predetermined value based on analysis of the shader; and   compiling the shader to include an enhanced sub-sequence based identification of the shader instruction as an origin of the predetermined value.   
     
     
         14 . The method of  claim 13 , comprising:
 evaluating at least one coordinate; and   determining whether the shader instruction can output the predetermined value based on the at least one coordinate.   
     
     
         15 . The method of  claim 13 , wherein the shader instruction comprises a sample_c instruction, a mul_sat instruction, an add_sat instruction, a ld instruction, a sample instruction, an AND instruction, a greater than instruction, an equal to instruction, or a less than instruction. 
     
     
         16 . The method of  claim 15 , wherein the predetermined value comprises one or more common values, the common values comprising one, zero, 1.0f, 0.0f, or the like. 
     
     
         17 . The method of  claim 13 , comprising:
 determining whether the shader instruction can be folded based on a determination that the shader instruction can output a predetermined value; and   compiling the shader instruction to include the enhanced sub-sequence based on a determination that the shader instruction can be folded.   
     
     
         18 . The method of  claim 13 , comprising compiling the shader instruction omitting the enhanced sub-sequence. 
     
     
         19 . The method of  claim 13 , comprising:
 determining whether an output-merger (OM) state of the shader instruction is set to a src_alpha; and   compiling the shader instruction to include the enhanced sub-sequence based on a determination that the OM state is set to src_alpha.   
     
     
         20 . At least one machine-readable, non-transitory storage medium comprising instructions that when executed by a computing device, cause the computing device to:
 identify a shader instruction as an origin of a predetermined value based on analysis of the shader; and   compile the shader to include an enhanced sub-sequence to process an output of the predetermined value by the shader instruction, based on identification of the shader instruction as an origin of the predetermined value.   
     
     
         21 . The at least one machine-readable, non-transitory storage medium of  claim 20 , comprising instructions that when executed by the computing device, cause the computing device to:
 evaluate at least one coordinate; and   determine whether the shader instruction can output the predetermined value based on the at least one coordinate.   
     
     
         22 . The at least one machine-readable, non-transitory storage medium of  claim 20 , wherein the shader instruction comprises a sample_c instruction, a mul_sat instruction, an add_sat instruction, a ld instruction, a sample instruction, an AND instruction, a greater than instruction, an equal to instruction, or a less than instruction. 
     
     
         23 . At least one machine-readable, non-transitory storage medium comprising instructions that when executed by a graphics processing unit (GPU), cause the GPU to:
 evaluate at least one coordinate of pixel;   execute a shader instruction based on the at least one coordinate;   determine whether an output of the shader instruction equals a predetermined value; and   execute a first sequence based on a determination that the output equals the predetermined value; or   execute a second sequence based on a determination that the output does not equal the predetermined value.   
     
     
         24 . The at least one machine-readable, non-transitory storage medium of  claim 23 , comprising instruction that when executed by the GPU, wherein the shader instruction comprises a sample_c instruction, a mul_sat instruction, an add_sat instruction, a ld instruction, a sample instruction, an AND instruction, a greater than instruction, an equal to instruction, or a less than instruction. 
     
     
         25 . The at least one machine-readable, non-transitory storage medium of  claim 23 , comprising instruction that when executed by the GPU, wherein the predetermined value comprises one or more common values, the common values comprising one, zero, 1.0f, 0.0f, or the like.

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