Apparatus and methods for vector operations

Abstract

Aspects for vector operations in neural network are described herein. The aspects may include a vector caching unit configured to store a first vector and a second vector, wherein the first vector includes one or more first elements and the second vector includes one or more second elements. The aspects may further include a computation module that includes one or more bitwise processors and a combiner. The bitwise processors may be configured to perform bitwise operations between each of the first elements and a corresponding one of the second elements to generate one or more operation results. The combiner may be configured to combine the one or more operation results into an output vector.

We claim: 
     
         1 . An apparatus for vector operations in a neural network, comprising:
 a controller unit configured to receive a vector bitwise operation instruction that indicates a first address of the first vector and a second address of a second vector; and   a computation module configured to receive the first vector and the second vector based on the first address and the second address in response to the vector bitwise operation instruction, wherein the first vector includes one or more first elements and the second vector includes one or more second elements, and wherein the computation module includes:
 one or more bitwise processors configured to perform bitwise operations between each of the first elements and a corresponding one of the second elements to generate one or more operation results, and 
 a combiner configured to combine the one or more operation results into an output vector. 
   
     
     
         2 . The apparatus of  claim 1 , wherein the vector bitwise operation instruction includes one or more register IDs that identify one or more registers configured to store the first address of the first vector, the second address of the second vector, a length of the first vector, and a length of the second vector. 
     
     
         3 . The apparatus of  claim 1 , further comprising one or more registers configured to store a length of the first vector and a length of the second vector. 
     
     
         4 . The apparatus of  claim 3 , further comprising a direct memory access unit configured to retrieve the first vector and the second vector from a storage device based on the starting address of the first vector, the length of the first vector, the starting address of the second vector, and the length of the second vector. 
     
     
         5 . The apparatus of  claim 1 , wherein the one or more bitwise processors are configured to perform a logical AND operation between each of the first elements and a corresponding one of the second elements to generate the one or more operation results when the vector bitwise operation instruction includes an operation code that indicates an AND operation between the first vector and the second vector. 
     
     
         6 . The apparatus of  claim 1 , wherein the one or more bitwise processors are configured to perform a logical OR operation between each of the first elements and a corresponding one of the second elements to generate the one or more operation results when the vector bitwise operation instruction includes an operation code that indicates an OR operation between the first vector and the second vector. 
     
     
         7 . An apparatus for vector operations in a neural network, comprising:
 a controller unit configured to receive a vector bitwise operation instruction that includes an address of a vector;   a computation module configured to receive the vector that includes one or more elements based on the address of the vector included in the vector bitwise operation instruction, wherein the computation module includes one or more bitwise processors configured to perform bitwise operations to the one or more elements to generate an output result.   
     
     
         8 . The apparatus of  claim 7 , wherein the vector bitwise operation instruction includes one or more register IDs that identify one or more registers configured to store the address of the vector and a length of the vector. 
     
     
         9 . The apparatus of  claim 7 , further comprising one or more registers configured to store a length of the first vector. 
     
     
         10 . The apparatus of  claim 9 , further comprising a direct memory access unit configured to retrieve the vector from a storage device based on the starting address of the vector and the length of the first vector. 
     
     
         11 . The apparatus of  claim 7 , wherein the one or more bitwise processors are configured to perform a logical AND operation to the one or more elements in the vector to generate the output result when the vector bitwise operation instruction includes an operation code that indicates an AND operation between the elements of the vector. 
     
     
         12 . The apparatus of  claim 7 , wherein the one or more bitwise processors are configured to perform a logical OR operation to the one or more elements in the vector to generate the output result when the vector bitwise operation instruction includes an operation code that indicates an OR operation between the elements of the vector. 
     
     
         13 . A method for vector operations in a neural network, comprising:
 receiving, by a controller unit, a vector bitwise operation instruction that indicates a first address of the first vector and a second address of a second vector;   receiving, by a computation module, the first vector and the second vector based on the first address and the second address in response to the vector bitwise operation instruction, wherein the first vector includes one or more first elements and the second vector includes one or more second elements;   performing, by one or more bitwise processors of the computation module, bitwise operations between each of the first elements and a corresponding one of the second elements to generate one or more operation results; and   combining, by a combiner of the computation module, the one or more operation results into an output vector.   
     
     
         14 . The method of  claim 13 , wherein the vector bitwise operation instruction includes one or more register IDs that identify one or more registers configured to store the first address of the first vector, the second address of the second vector, a length of the first vector, and a length of the second vector. 
     
     
         15 . The method of  claim 13 , further comprising storing, by one or more registers, a length of the first vector and a length of the second vector. 
     
     
         16 . The method of  claim 15 , further comprising retrieving, by a direct memory access unit, the first vector and the second vector from a storage device based on the starting address of the first vector, the length of the first vector, the starting address of the second vector, and the length of the second vector. 
     
     
         17 . The method of  claim 13 , further comprising performing, by the one or more bitwise processors, a logical AND operation between each of the first elements and a corresponding one of the second elements to generate the one or more operation results when the vector bitwise operation instruction includes an operation code that indicates an AND operation between the first vector and the second vector. 
     
     
         18 . The method of  claim 13 , further comprising performing, by the one or more bitwise processors, a logical OR operation between each of the first elements and a corresponding one of the second elements to generate the one or more operation results when the vector bitwise operation instruction includes an operation code that indicates an OR operation between the first vector and the second vector. 
     
     
         19 . A method for vector operations in a neural network, comprising:
 receiving, by a controller unit, a vector bitwise operation instruction that includes an address of a vector;   receiving, by a computation module, the vector that includes one or more elements based on the address of the vector included in the vector bitwise operation instruction; and   performing, by one or more bitwise processors of the computation module, bitwise operations to the one or more elements to generate an output result.   
     
     
         20 . The method of  claim 19 , wherein the vector bitwise operation instruction includes one or more register IDs that identify one or more registers configured to store the address of the vector and a length of the vector. 
     
     
         21 . The method of  claim 19 , further comprising storing, by one or more registers a length of the first vector. 
     
     
         22 . The method of  claim 21 , further comprising retrieving, by a direct memory access unit, the vector from a storage device based on the starting address of the vector and the length of the first vector. 
     
     
         23 . The method of  claim 19 , wherein the performing bitwise operations further comprises performing, by the one or more bitwise processors, a logical AND operation to the one or more elements in the vector to generate the output result when the vector bitwise operation instruction includes an operation code that indicates an AND operation between the elements of the vector. 
     
     
         24 . The method of  claim 19 , wherein the performing bitwise operations further comprises performing, by the one or more bitwise processors, a logical OR operation to the one or more elements in the vector to generate the output result when the vector bitwise operation instruction includes an operation code that indicates an OR operation between the elements of the vector.