Providing code sections for matrix of arithmetic logic units in a processor

Abstract

The present invention relates to a processor having a trace cache and a plurality of ALUs arranged in a matrix, comprising an analyser unit located between the trace cache and the ALUs, wherein the analyser unit analyses the code in the trace cache, detects loops, transforms the code, and issues to the ALUs sections of the code combined to blocks for joint execution for a plurality of clock cycles.

1 . A processor comprising:
 an instruction fetcher operative to fetch instructions;   an instruction issue unit operative to issue the fetched instructions;   at least one load unit operative to load data by performing load instructions received from the issue unit;   an arrangement of at least two arithmetic units operative to execute arithmetic instructions received from the issue unit; and   a register file operative to store data for processing by the arrangement,   wherein
 the at least two arithmetic execution units are encapsulated to provide execution within a capsule so that the data is processed by the at least two arithmetic execution units solely depending on a clock signal used by the processor, 
 the at least one load unit is located outside the capsule, and 
 data availability is determined outside the capsule so that the execution within the capsule is enabled once all data outside the capsule is available, and wherein 
 the instruction issue unit is operative to issue the load instructions separated from the arithmetic instructions, such that
 a block of arithmetic instructions is issued for execution in the arrangement, and 
 load instructions are issued for execution by the at least one load unit, 
 
 such that all load data is available to the at least two arithmetic execution units before starting execution of the block of arithmetic instructions.