Burst length defined page size and related methods

Abstract

In some examples, a memory device is configured with a reduced command set and a variable burst length. In some instances, the variable burst length defines a page size associated with data to be loaded into a cache. In other instances, the variable burst length may be set on the fly per read/write command and, in some cases, the burst length may be utilized to define the page size associated with the read/write command.

1 - 20 . (canceled) 
     
     
         21 . A method comprising:
 receiving, at a magnetic memory device, a command from an external source, wherein the command includes a predetermined series of commands;   in response to the command, opening a page associated with a memory bank;   determining a row address, the row address indicating the page associated with the memory bank;   determining a burst length based at least in part on a first mode selector bit, wherein the burst length defines a page size associated with a read or write command;   determining a starting position within the page associated with the memory bank based at least in part on a second mode selector bit, the starting position indicating a first bit to load into a cache; and   loading a number of bits starting with the first bit into the cache, the number of bits equal to the burst length.   
     
     
         22 . The method as recited in  claim 21 , wherein the predetermined series of commands is at least one of:
 an activate-read-precharge command;   an activate-write-precharge command; or   an activate-read-modify-write-precharge command.   
     
     
         23 . The method as recited in  claim 21 , wherein the burst length is determined based at least in part on one of the following:
 a fuse programmable register;   an initialization register; or   a mode register set in response to at least one mode selector bit associated with the predetermined series of commands.   
     
     
         24 . The method as recited in  claim 21 , wherein the burst length is determined based at least in part on a number of independently activatable banks associated with the magnetic memory device. 
     
     
         25 . The method as recited in  claim 21 , wherein the burst length is selected from a group of predetermined burst lengths associated with the magnetic memory device. 
     
     
         26 . The method as recited in  claim 21 , wherein the first bit is between a first bit of the page and a last bit of the page. 
     
     
         27 . The method as recited in  claim 21 , wherein the burst length is configured to reduce energy consumption during a self-referencing read operation. 
     
     
         28 . An electronic device comprising:
 a magnetic memory device including:
 multiple memory banks; 
 multiple page access circuits, wherein each page access circuit of the multiple page access circuits is associated with at least one memory bank of the plurality of memory banks, and wherein each page access circuit of the multiple page access circuits is configured to allow each memory bank of the magnetic memory device to activate independently of the other memory banks; and 
 a cache configured to receive data stored in at least one memory bank of the multiple memory banks; and 
   an external source coupled to the magnetic memory device and the cache, wherein the external source is configured to (i) issue a command to the magnetic memory device, wherein the command includes a predetermined series of commands, and (ii) access data loaded into the cache, wherein the command causes the magnetic memory device to open a page and load data stored in the at least one memory bank into the cache, wherein the predetermined series of commands includes a first mode selector bit configured to identify a starting position within the at least one memory bank, and wherein the predetermined series of commands includes a second mode selector bit to define a variable burst length.   
     
     
         29 . The electronic device as recited in  claim 28 , wherein the starting position identifies a first bit within a page to load into the cache. 
     
     
         30 . The electronic device as recited in  claim 29 , wherein the first bit is between a first bit of the page and a last bit of the page. 
     
     
         31 . The electronic device as recited in  claim 28 , wherein the predetermined series of commands is at least one of:
 an activate-read-precharge command;   an activate-write-precharge command; or   an activate-read-modify-write-precharge command.   
     
     
         32 . The electronic device as recited in  claim 28 , wherein the starting position is between a first bit of the page and a last bit of the page. 
     
     
         33 . A magnetic memory device comprising:
 multiple memory banks;   page access circuitry coupled to the multiple memory banks and configured to:
 receive a command from an external source, wherein the command includes a predetermined series of commands, wherein the predetermined series of commands includes a first mode selector bit configured to identify a first bit within a page to load into cache bits, and wherein the predetermined series of commands includes a second mode selector bit to define a page size associated with the magnetic memory device; 
 open the page, and load the defined page size into cache bits in response to receiving the command; and 
   at least one register, a value of the register indicating a burst length associated with the magnetic memory device, wherein the burst length is based at least in part on a first size of individual memory banks of the multiple memory banks, and wherein the burst length defines the page size associated with the magnetic memory device.   
     
     
         34 . The magnetic memory device as recited in  claim 33 , wherein an amount of data loaded into the cache bits is a multiple of the first size of individual ones of the multiple memory banks. 
     
     
         35 . The magnetic memory device as recited in  claim 33 , wherein an amount of the data loaded into the cache bits is based at least on the page size. 
     
     
         36 . The magnetic memory device as recited in  claim 33 , wherein the burst length is a first burst length or a second burst length, the first burst length defining a page size of the first size and the second burst length defining a page size that is twice the first size. 
     
     
         37 . The magnetic memory device as recited in  claim 36 , wherein:
 the predetermined series of commands includes an address of a first number of bits when the burst length is the first burst length; and   the predetermined series of commands includes an address of less than the first number of bits when the burst length is the second burst length.   
     
     
         38 . The magnetic memory device as recited in  claim 33 , wherein the register is at least one of:
 a fuse programmable register set during assembly of the magnetic memory device;   an initialization register set during initialization of the magnetic memory device; or   a mode register set in response to receiving the command.   
     
     
         39 . The magnetic memory device as recited in  claim 33 , wherein the page access circuitry includes dedicated page access circuitry for each of the multiple memory banks, and each of the multiple memory banks may be activated independently from other memory banks of the multiple memory banks. 
     
     
         40 . The magnetic memory device as recited in  claim 33 , wherein the predetermined series of commands is at least one of:
 an activate-read-precharge command;   an activate-write-precharge command; or   an activate-read-modify-write-precharge command.