Methods and systems for transferring data between a processing device and external devices

Abstract

At the inputs and/or outputs, memories are assigned to a reconfigurable module to achieve decoupling of internal data and in particular decoupling of the reconfiguration cycles from the external data streams (to/from peripherals, memories, etc.)

What is claimed is: 
     
         1 . A method, comprising:
 providing a plurality of data processors;   providing a plurality of applications each identified by an APID;   associating respective one or more of said plurality of data processors with said one or more of said plurality or applications;   providing a memory; and   communicating data to and from said memory and said plurality of data processors according to said APID.   
     
     
         2 . The method according to  claims 1  wherein said memory is composed of a plurality of separately addressable pages and further wherein said APID is used to address individual pages. 
     
     
         3 . The method according to  claim 1  wherein said memory comprises a plurality of different memories and said APID is used to address individual memories. 
     
     
         4 . The method according to  claim 1  wherein the higher order bits of an address addresses different memories 
     
     
         5 . The method according to  claim 1  wherein said plurality of applications are processed in parallel. 
     
     
         6 . The method of  claim 1  where the memory is located on the same physical chip as the plurality of data processors. 
     
     
         7 . The method according to  claim 6 , wherein the memory comprises a plurality of separately addressable memories. 
     
     
         8 . A device for data processing, comprising:
 a field of reconfigurable modules; and   an interface module configured for an exchange of data to be processed between the field of reconfigurable modules and an external circuit configuration, wherein the interface module includes at least one FIFO memory in which data may be stored and from which data may be retrieved.   
     
     
         9 . The device as recited in  claim 8 , further comprising:
 a circuit configuration to determine data which will be needed in a future configuration and to preloading the determined data into the interface configuration.   
     
     
         10 . The device according to  claim 9 , wherein the circuit configuration includes a memory area addressable rapidly via the interface module. 
     
     
         11 . The device as recited in  claim 10 , wherein the rapidly addressable memory area includes at least one of a cache memory, an external RAM, a FIFO memory, and a register. 
     
     
         12 . The device as recited in  claim 8 , further comprising:
 means for backing up data of a configuration which has previously been executed and is at least partially no longer active at the time of data retrieval, the configuration data already canceled by reconfiguration of participating field elements.   
     
     
         13 . The device as recited in  claim 8 , further comprising:
 means for backing up data of a configuration which has previously been executed and is at least partially no longer active at the time of data retrieval, for at least one of preventing deletion, and overwriting of data already sent once but not yet known to have been satisfactorily received.   
     
     
         14 . The device as recited in  claim 8 , further comprising:
 at least one multiple field elements and field elements grouped into configurations of addressable memories to store data at least one of non-locally and temporarily.   
     
     
         15 . The device as recited in  claim 14 , wherein the addressable memory are RAM cells. 
     
     
         16 . A system, the system comprising:
 a plurality of processors;   a cache system comprising plurality of cache segments;   an interconnect system for interconnecting each of the cache segments with each of the processors; each of the processors with neighboring processors, and each of the segments with neighboring cache segments; and   at least one interface unit operable for transmitting data between the interconnect system and external devices via an external bus;   
     
     
         17 . The system of  claim 16 , wherein the interconnect system comprises an arbiter, the arbiter controlling processor access to the interconnect system. 
     
     
         18 . The system of  claim 17 , wherein the arbiter allows processor access in the chronological sequence. 
     
     
         19 . The system according to  claim 16 , wherein said at least one interface unit is to store and transmit data to external devices in packets via a buffer memory.