Multiply-Acumulate Circuits

Abstract

In some examples, a method may be performed by a multiply-accumulate circuit. As part of the method a row driver of the multiply-accumulate circuit may drive a row value line based on an input vector bit of an input vector received by the row driver. The row driver may also drive a row line that controls a corresponding memristor according to the input vector bit. The corresponding memristor may store a weight value bit of a weight value to apply to the input vector for a multiply-accumulate operation. The method may further include a sense amplifier generating an output voltage based on a current output from the corresponding memristor and counter circuitry adjusting a counter value that represents a running total of the multiply-accumulate operation based on the row value line, the output voltage generated by the sense amplifier, or a combination of both.

1 . A multiply-accumulate circuit comprising:
 a set of row driver circuits, wherein each row driver receives an input vector bit of an input vector;   a set of memristor circuits linked to the set of row driver circuits to form a set of rows, each row having a row driver which activates the row and a corresponding memristor circuit, wherein each memristor stores a weight value bit of a weight value to apply to the input vector for a multiply-accumulate operation;   a sense amplifier linked to the set of memristor circuits to apply an output voltage based on a current output from a memristor of the set of memristor circuits, the current output representative of the weight value bit stored by the memristor; and   counter circuitry to store a counter value and to adjust the counter value based on a row value output from the set of row driver circuits, the output voltage of the sense amplifier, or both.   
     
     
         2 . The circuit of  claim 1 , wherein a particular row driver and a corresponding memristor are active at a particular time; and
 wherein the counter circuitry adjusts the counter value by incrementing, decrementing, or taking no action based on the row value output from the particular row driver and the output voltage applied by the sense amplifier based on the current output of the corresponding memristor circuit.   
     
     
         3 . The circuit of  claim 2 , wherein the counter circuitry is to:
 increment the counter value when the input vector bit received by the particular row driver is a ‘1’ value and the corresponding memristor stores a ‘1’ value for the weight value bit;   decrement the counter value when the input vector bit received by the particular row driver is a ‘1’ value and the corresponding memristor stores a ‘0’ value for the weight value bit; and   take no action when the input vector bit received by the particular row driver is a ‘0’ value.   
     
     
         4 . The circuit of  claim 1 , wherein the counter circuitry stores the result of the multiply-accumulate operation between the input vector and the weight value after each row driver and corresponding memristor have been activated. 
     
     
         5 . The circuit of  claim 1 , wherein each memristor stores a ‘1’ value for the weight value bit when the memristor circuit is programmed to a low resistive state and stores a ‘0’ value for the weight bit when the memristor is programmed to a high resistive state. 
     
     
         6 . The circuit of  claim 5 , wherein:
 the ‘0’ value for the weight value bit represents an actual weight value of ‘−1’; and   the ‘1’ value for the weight value bit represents an actual weight value of ‘1’.   
     
     
         7 . The circuit of  claim 1 , wherein each row driver comprises bypass circuitry to bypass activation of the row driver when the input vector bit received by the row driver is a ‘0’ value. 
     
     
         8 . The circuit of  claim 7 , wherein the counter circuitry stores the result of the multiply-accumulate operation between the input vector and the weight value after activation of each row driver that receives an input vector bit having a ‘1’ value and corresponding memristor. 
     
     
         9 . The circuit of  claim 1 , wherein each row driver comprises a shift register initialized to a ‘0’ value; and
 further comprising a token propagation unit to propagate a ‘1’ value through the set of row driver circuits; and 
 wherein a particular row is activated when a shift register of the row driver of the particular row stores a ‘1’ value. 
 
     
     
         10 . The circuit of  claim 1 , wherein:
 a ‘0’ value for the input vector bit represents an actual input vector value of ‘−1’; and   a ‘1’ value for the input vector bit represents an actual input vector value of ‘1’; and   wherein the counter circuitry is to adjust the counter value when a particular row is activated by:
 incrementing the counter value when:
 both the row value output by a row driver of the particular row and the output voltage applied by the sense amplifier is a ‘0’ value; or 
 both the row value output by the row driver of the particular row and the output voltage applied by the sense amplifier is a ‘1’ value; and 
 
 decrementing the counter value when:
 the row value output by the row driver of the particular row is a ‘0’ value and the output voltage applied by the sense amplifier is a ‘1’ value; or 
 the row value output by the row driver of the particular row is a ‘1’ value and the output voltage applied by the sense amplifier is a ‘0’ value. 
 
   
     
     
         11 . A method comprising:
 driving, by a row driver of a multiply-accumulate circuit, a row value onto a row value line based on an input vector bit of an input vector received by the row driver;   driving, by the row driver, a row line that controls a corresponding memristor according to the input vector bit, the corresponding memristor storing a weight value bit of a weight value to apply to the input vector for a multiply-accumulate operation;   generating, by a sense amplifier, an output voltage based on a current output from the corresponding memristor; and   adjusting, by counter circuitry, a counter value that represents a running total of the multiply-accumulate operation based on the row value line, the output voltage generated by the sense amplifier, or a combination of both.   
     
     
         12 . The method of  claim 11 , wherein driving the row line comprises driving the row line high when the input vector bit has a value of ‘1’ and driving the row line low when the input vector bit has a value of ‘0’. 
     
     
         13 . The method of  claim 11 , further comprising:
 receiving, by the row driver, an activation token from a previous row driver in the multiply-accumulate circuit; and   driving the row line and the row value line responsive to receiving the activation token.   
     
     
         14 . The method of  claim 11 , wherein adjusting the counter value by the counter circuitry comprises:
 incrementing the counter value when the input vector bit received by the row driver is a ‘1’ value and the corresponding memristor stores a ‘1’ value for the weight value bit;   decrementing the counter value when the input vector bit received by the particular row driver is a ‘1’ value and the corresponding memristor stores a ‘0’ value for the weight value bit; and   taking no action when the input vector bit received by the particular row driver is a ‘0’ value.   
     
     
         15 . The method of  claim 11 , wherein:
 a ‘0’ value for the input vector bit represents an actual input vector value of ‘−1’; and   a ‘1’ value for the input vector bit represents an actual input vector value of ‘1’; and   wherein the adjusting the counter value by the counter circuitry comprises:
 incrementing the counter value when:
 both the row value driven by the row driver and the output voltage generated by the sense amplifier is a ‘0’ value; or 
 both the row value driven by the row driver and the output voltage generated by the sense amplifier is a ‘1’ value; and 
 
 decrementing the counter value when:
 the row value driven by the row driver is a ‘0’ value and the output voltage generated by the sense amplifier is a ‘1’ value; or 
 the row value driven by the row driver is a ‘1’ value and the output voltage generated by the sense amplifier is a ‘0’ value. 
 
   
     
     
         16 . The method of  claim 11 , wherein driving the row line according to the input vector bit comprises:
 driving the row line high with a memristor read voltage when the input vector bit is a ‘1’ value and an activation token propagated through the multiply-accumulate circuit is latched by a shift register of the row driver; and   causing the row line to float otherwise.   
     
     
         17 . A multiply-accumulate circuit comprising:
 a set of row driver circuits, wherein each row driver receives an input vector bit of an input vector;   a first circuitry column comprising:
 a first set of memristor circuits linked to the set of row driver circuits to form in part a set of rows, each row having a row driver which activates the row and a corresponding memristor circuit of the first set of memristor circuits, the first set of memristor circuits programmed with a first weight value; 
 a sense amplifier linked to the first set of memristor circuits to apply an output voltage based on a current output from a memristor of the first set of memristor circuits, the current output representative of a weight value bit stored by the memristor; and 
 counter circuitry to store a first counter value and to adjust the first counter value based on a row value output from the set of row driver circuits, the output voltage of the sense amplifier of the first circuitry column, or both; and 
   a column circuitry column comprising:
 a second set of memristor circuits also linked to the set of row driver circuits to form in part the set of rows, each row a corresponding memristor circuit of the second set of memristor circuits, the second set of memristor circuits programmed with a second weight value different from the first weight value; 
 a sense amplifier linked to the second set of memristor circuits to apply an output voltage based on a current output from a memristor of the second set of memristor circuits, the current output representative of a weight value bit stored by the memristor; and 
 counter circuitry to store a second counter value and to adjust the second counter value based on a row value output from the set of row driver circuits, the output voltage of the sense amplifier of the second circuitry column, or both. 
   
     
     
         18 . The multiply-accumulate circuit of  claim 17 , wherein the first circuitry column and the second circuitry column operate in parallel to compute results of a first multiply-accumulate operation between the input vector and the first weight value and a second multiply-accumulate operation between the input vector and the second weight value. 
     
     
         19 . The multiply-accumulate circuit of  claim 17 , wherein a particular row driver controls both a corresponding memristor in the first set of memristor circuits and another corresponding memristor in the second set of memristor circuits. 
     
     
         20 . The multiply-accumulate circuit of  claim 17 , wherein:
 the counter circuitry of the first circuitry column stores a result of a first multiply-accumulate operation between the input vector and the first weight value after activation of each row driver that receives an input vector bit having a ‘1’ value; and   the counter circuitry of the second circuitry column stores a result of a second multiply-accumulate operation between the input vector and the second weight value after activation of each of the row driver that receives an input vector bit having a ‘1’ value.