Access device and phase change memory combination structure in backend of line (beol)

Abstract

A combined semiconductor device is fabricated by forming a first access structure from a mixed ionic electronic conduction (MIEC) material. A first side of a first memory structure is electrically coupled with a first side of the first access structure to form the combination device. A subtractive etching process is applied to the combination device such that a surface of the combination device that is substantially orthogonal to a plane of a substrate of the semiconductor device is within a defined tapering tolerance.

1 . A semiconductor device comprising:
 a first access structure formed from a mixed ionic electronic conduction (MIEC) material;   a first side of a first memory structure electrically coupled with a first side of the first access structure to form a combination device, wherein a subtractive etching process is applied to the combination device such that a surface of the combination device that is substantially orthogonal to a plane of a substrate of the semiconductor device is within a defined tapering tolerance;   a pore in a dielectric material deposited over the first access structure, the pore comprising a tapered hole extended through the dielectric material; and   an electrode formed by filling an electrode material in the pore, wherein the pore is configured to enable an electrical coupling between a first end of the electrode and the first access structure, and wherein the first memory structure is formed such that the first surface of the first memory structure is in an electrical coupling with a second end of the electrode.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the subtractive etching process is a single step in the fabrication process. 
     
     
         3 . The semiconductor device of  claim 1 , further comprising:
 a first electrode electrically coupled with a second side of the first access structure; and   a second electrode electrically coupled with a second side of the first memory structure.   
     
     
         4 . The semiconductor device of  claim 1 , further comprising:
 a Phase-Change memory (PCM) material forming the first memory structure filled in the pore, wherein the pore is configured to enable an electrical coupling between the first memory structure and the first access structure.   
     
     
         5 . (canceled) 
     
     
         6 . The semiconductor device of  claim 1 , further comprising:
 a second access structure formed from the MIEC material stacked on a second side of the memory structure, wherein the second side of the first memory structure is electrically coupled with a second side of the second access structure; and   a first side of a second memory structure electrically coupled with a first side of the second access structure.   
     
     
         7 . The semiconductor device of  claim 1 , further comprising:
 a first electrode electrically coupled with a second side of the first access structure; and   a second electrode electrically coupled with a second side of the second memory structure.   
     
     
         8 . A method comprising:
 forming, using a semiconductor fabrication system, a first access structure from a mixed ionic electronic conduction (MIEC) material;   electrically coupling a first side of a first memory structure with a first side of the first access structure to form a combination device; and   
       applying a subtractive etching process is applied to the combination device such that a surface of the combination device that is substantially orthogonal to a plane of a substrate of the semiconductor device is within a defined tapering tolerance. 
     
     
         9 . The method of  claim 8 , wherein the subtractive etching process is a single step in the fabrication process. 
     
     
         10 . The method of  claim 8 , further comprising:
 electrically coupling a first electrode with a second side of the first access structure; and   electrically coupling a second electrode with a second side of the first memory structure.   
     
     
         11 . The method of  claim 8 , further comprising:
 forming a pore in a dielectric material over the first access structure; and   filling a Phase-Change memory (PCM) material in the pore to form the first memory structure, wherein the pore is configured to enable an electrical coupling between the first memory structure and the first access structure.   
     
     
         12 . The method of  claim 8 , further comprising:
 forming a pore in a dielectric material over the first access structure;   filling an electrode material in the pore to form an electrode, wherein the pore is configured to enable an electrical coupling between a first end of the electrode and the first access structure, and wherein the first memory structure is formed such that the first surface of the first memory structure is in an electrical coupling with a second end of the electrode.   
     
     
         13 . The method of  claim 8 , further comprising:
 forming a second access structure from the MIEC material stacked on a second side of the memory structure, wherein the second side of the first memory structure is electrically coupled with a second side of the second access structure; and   electrically coupling a first side of a second memory structure with a first side of the second access structure.   
     
     
         14 . The method of  claim 8 , further comprising:
 electrically coupling a first electrode with a second side of the first access structure; and   electrically coupling a second electrode with a second side of the second memory structure.   
     
     
         15 . A semiconductor fabrication system comprising a processor, a computer-readable memory, and a computer-readable storage device, and program instructions stored on the storage device for execution by the processors via the memories, the stored program instructions causing the fabrication system to perform operations comprising:
 forming a first access structure from a mixed ionic electronic conduction (MIEC) material;   electrically coupling a first side of a first memory structure with a first side of the first access structure to form a combination device; and   
       applying a subtractive etching process is applied to the combination device such that a surface of the combination device that is substantially orthogonal to a plane of a substrate of the semiconductor device is within a defined tapering tolerance. 
     
     
         16 . The semiconductor fabrication system of  claim 15 , wherein the subtractive etching process is a single step in the fabrication process. 
     
     
         17 . The semiconductor fabrication system of  claim 15 , further comprising:
 electrically coupling a first electrode with a second side of the first access structure; and   electrically coupling a second electrode with a second side of the first memory structure.   
     
     
         18 . The semiconductor fabrication system of  claim 15 , further comprising:
 forming a pore in a dielectric material over the first access structure; and   filling a Phase-Change memory (PCM) material in the pore to form the first memory structure, wherein the pore is configured to enable an electrical coupling between the first memory structure and the first access structure.   
     
     
         19 . The semiconductor fabrication system of  claim 15 , further comprising:
 forming a pore in a dielectric material over the first access structure;   filling an electrode material in the pore to form an electrode, wherein the pore is configured to enable an electrical coupling between a first end of the electrode and the first access structure, and wherein the first memory structure is formed such that the first surface of the first memory structure is in an electrical coupling with a second end of the electrode.   
     
     
         20 . The semiconductor fabrication system of  claim 15 , further comprising:
 forming a second access structure from the MIEC material stacked on a second side of the memory structure, wherein the second side of the first memory structure is electrically coupled with a second side of the second access structure; and   electrically coupling a first side of a second memory structure with a first side of the second access structure.