Processor For Implementing Mathematical Functions or Models

Abstract

A processor comprises an array of computing elements, with each computing element comprising an arithmetic logic circuit (ALC) and at least one three-dimensional memory (3D-M) array. The 3D-M array stores at least a portion of a look-up table (LUT) for a non-arithmetic function, while the ALC performs arithmetic operations on the LUT data.

What is claimed is: 
     
         1 . A processor for implementing a mathematical function, comprising:
 at least first and second memory arrays on a memory level, wherein said first memory array stores at least a first portion of a first look-up table (LUT) for a first mathematical function; and, said second memory array stores at least a second portion of a second LUT for a second mathematical function;   at least an arithmetic logic circuit (ALC) on a logic level for performing at least an arithmetic operation on selected data from said first LUT or said second LUT, wherein said logic level is a different physical level than said memory level; and   means for communicatively coupling said memory level and said logic level;   wherein said mathematical function is a combination of at least said first and second mathematical functions; and, each of said first and second mathematical functions includes more operations than arithmetic operations performable by said ALC.   
     
     
         2 . The processor according to  claim 1 , further comprising a semiconductor substrate, wherein said logic level is disposed on said semiconductor substrate; said memory level is disposed above said substrate; and, said logic level and said memory level are communicatively coupled by a plurality of contact vias. 
     
     
         3 . The processor according to  claim 2 , wherein said first memory array is a first three-dimensional memory (3D-M) array; and, said second memory array is a second 3D-M array. 
     
     
         4 . The processor according to  claim 3 , wherein said first or second 3D-M array at least partially covers said ALC. 
     
     
         5 . The processor according to  claim 1 , wherein said first LUT includes the functional values of said mathematical function; and, said second LUT includes the derivative values of said mathematical function. 
     
     
         6 . The processor according to  claim 1 , wherein said mathematical function is a composite function of said first and second mathematical functions. 
     
     
         7 . The processor according to  claim 1 , wherein said ALC comprises at least an adder, a multiplier, or a multiply-accumulator (MAC). 
     
     
         8 . The processor according to  claim 1 , wherein said ALC comprises at least a pre-processing circuit and/or a post-processing circuit. 
     
     
         9 . The processor according to  claim 1 , wherein said arithmetic operations performable by said ALC consist of addition, subtraction and multiplication. 
     
     
         10 . The processor according to  claim 1 , wherein said processor is a micro-controller, a controller, a central processing unit (CPU), a digital signal processor (DSP), a graphic processing unit (GPU), a network-security processor, an encryption/decryption processor, an encoding/decoding processor, a neural-network processor, or an artificial intelligence (AI) processor. 
     
     
         11 . A processor for simulating a system including a system component, comprising:
 at least a memory array for storing at least a portion of a look-up table (LUT) for a mathematical model of said system component;   at least an arithmetic logic circuit (ALC) for performing at least an arithmetic operation on selected data from said LUT; and   means for communicatively coupling said memory array and said ALC;   wherein said mathematical model cannot be represented by a combination of arithmetic operations performable by said ALC.   
     
     
         12 . The processor according to  claim 11 , wherein said memory array is disposed on a memory level; said ALC is disposed on a logic level; said memory level and said logic level are different physical levels. 
     
     
         13 . The processor according to  claim 11 , further comprising a semiconductor substrate, wherein said ALC is disposed on said semiconductor substrate; said memory array is disposed above said substrate; and, said ALC and said memory array are communicatively coupled by a plurality of contact vias. 
     
     
         14 . The processor according to  claim 13 , wherein said memory array is a three-dimensional memory (3D-M) array. 
     
     
         15 . The processor according to  claim 11 , wherein said LUT includes at least raw measurement data. 
     
     
         16 . The processor according to  claim 11 , wherein said LUT includes at least smoothed measurement data. 
     
     
         17 . The processor according to  claim 11 , wherein said ALC comprises at least an adder, a multiplier, or a multiply-accumulator (MAC). 
     
     
         18 . The processor according to  claim 11 , wherein said ALC comprises at least a pre-processing circuit and/or a post-processing circuit. 
     
     
         19 . The processor according to  claim 11 , wherein said arithmetic operations performable by said ALC consist of addition, subtraction and multiplication. 
     
     
         20 . The processor according to  claim 11 , wherein said processor is a micro-controller, a controller, a central processing unit (CPU), a digital signal processor (DSP), a graphic processing unit (GPU), a network-security processor, an encryption/decryption processor, an encoding/decoding processor, a neural-network processor, or an artificial intelligence (AI) processor.