High and low voltage limited power amplification system

Abstract

Cascode power amplifier with voltage limiter. A power amplification system can include an input transistor having an input transistor gate configured to receive a radio-frequency (RF) signal, an input transistor source coupled to a ground voltage, and an input transistor drain. The power amplification can further include an output transistor having an output transistor drain configured to output an amplified version of the RF signal, an output transistor gate coupled to a bias voltage, and an output transistor source. The power amplification system can further include a high voltage limiter coupled between the output transistor drain and output transistor gate. The high voltage limiter can be configured to prevent a gate-drain voltage of the output transistor from exceeding a high voltage threshold.

1 . A method for amplifying radio-frequency (RF) signals, the method comprising:
 receiving an input signal at a signal input terminal;   generating an amplified output signal at a signal output terminal;   receiving a supply voltage from a supply voltage terminal;   receiving one or more bias voltages at one or more bias terminals;   amplifying the input signal using a signal amplifier coupled to the signal input terminal, the signal output terminal, the supply voltage terminal, and the one or more bias terminals, the signal amplifier having a plurality of transistors biased by the one or more bias voltages including an input transistor, an output transistor, and one or more middle transistors; and   limiting voltages across one or more of the plurality of transistors using a voltage limitation system to prevent voltages from exceeding a high voltage threshold.   
     
     
         2 . The method of  claim 1  wherein the high voltage threshold is a breakdown voltage of the one or more of the plurality of transistors. 
     
     
         3 . The method of  claim 2  wherein limiting voltages comprises preventing a gate-drain voltage of the output transistor from exceeding a breakdown voltage of the output transistor. 
     
     
         4 . The method of  claim 1  further comprising providing one of a plurality of bias sources for a gate of the output transistor. 
     
     
         5 . The method of  claim 4  further comprising providing one of a plurality of bias sources for gates of the one or more middle transistors. 
     
     
         6 . The method of  claim 5  wherein providing one of the plurality of bias sources for the gates of the one or more middle transistors prevents a gate-drain voltage of the one or more middle transistors from exceeding a breakdown voltage. 
     
     
         7 . The method of  claim 5  further comprising attenuating the amplified output signal to provide the one of a plurality of bias sources of the one or more middle transistors. 
     
     
         8 . The method of  claim 1  wherein limiting voltages across the one or more of the plurality of transistors further comprises preventing voltages from dropping below a low voltage threshold. 
     
     
         9 . The method of  claim 8  wherein the low voltage threshold is a bias voltage that places the one or more of the plurality of transistors in an active mode. 
     
     
         10 . The method of  claim 8  wherein preventing voltages from dropping below the low voltage threshold comprises maintaining a middle transistor coupled to the input transistor in an active mode. 
     
     
         11 . The method of  claim 8  further comprising providing one of a plurality of bias sources for a gate of a middle transistor coupled to the input transistor.