Thin film transistor, display device, and thin film transistor manufacturing method

Abstract

Provided are a thin film transistor, a display device, and a thin film transistor manufacturing method, in which variation in characteristics is small. The present invention is provided with: a gate electrode formed on a substrate; a gate insulation film formed so as to cover the gate electrode; a semiconductor layer which is formed on the upper side of the gate insulation film and which includes a polysilicon layer disposed, in a plan view, inside a region defined by the gate electrode; an etching stopper layer disposed on the upper side of the polysilicon layer; and a source electrode and a drain electrode provided on the semiconductor layer so as to be separated from each other, wherein the polysilicon layer has first and second regions which are not covered with the etching stopper layer, and a part of the source electrode exists above the first region and a part of the drain electrode exists above the second region.

1 . A thin film transistor comprising:
 a gate electrode disposed on a substrate;   a gate insulating film covering the gate electrode;   a semiconductor layer disposed on the gate insulating film, the semiconductor layer including a polysilicon film located within a range defined by the gate electrode in a plan view;   an etch stop layer disposed on the polysilicon film; and   a source electrode and a drain electrode disposed on the semiconductor layer with a space therebetween, wherein   the polysilicon film has first and second regions that are not covered by the etch stop layer,   a portion of the source electrode is located over the first region, and a portion of the drain electrode is located over the second region, and   the semiconductor layer includes an amorphous silicon film in the same layer as the polysilicon film.   
     
     
         2 . The thin film transistor according to  claim 1 , wherein
 the first and second regions of the polysilicon film are located outside a range defined by the etch stop layer in a plan view.   
     
     
         3 . The thin film transistor according to  claim 1 , wherein
 the first and second regions of the polysilicon film are located within a range defined by the etch stop layer in a plan view.   
     
     
         4 . The thin film transistor according to  claim 1 , wherein the first and second regions each have a length of at least 3 μm in a direction in which the source electrode and the drain electrode are spaced. 
     
     
         5 . (canceled) 
     
     
         6 . A display apparatus comprising:
 a plurality of display elements; and   a plurality of thin film transistors configured to select or drive the respective display elements, wherein   each of the thin film transistors is the thin film transistor according to  claim 1 , and   each of the thin film transistors selects or drives the corresponding display element when the display element is to be displayed.   
     
     
         7 . A method for manufacturing a thin film transistor, comprising:
 forming a gate electrode on a substrate;   forming a gate insulating film to cover the gate electrode;   forming a semiconductor layer on the gate insulating film, the semiconductor layer including an amorphous silicon film;   forming an etch stop layer on the semiconductor layer;   forming a polysilicon film within a range defined by the gate electrode in a plan view by irradiating a portion of the amorphous silicon film with energy beams from above through the etch stop layer;   removing portions of the etch stop layer so that the polysilicon film has first and second regions that are not covered by the etch stop layer; and   forming a source electrode and a drain electrode on the semiconductor layer with a space therebetween so that a portion of one of the source electrode and the drain electrode is located over the first region, and a portion of another of the source electrode and the drain electrode is located over the second region.   
     
     
         8 . A method for manufacturing a thin film transistor, comprising:
 forming a gate electrode on a substrate;   forming a gate insulating film to cover the gate electrode;   forming a semiconductor layer on the gate insulating film, the semiconductor layer including an amorphous silicon film;   forming a polysilicon film within a range defined by the gate electrode in a plan view by irradiating a portion of the amorphous silicon film with energy beams;   forming an etch stop layer on the semiconductor layer;   removing portions of the etch stop layer so that the polysilicon film has first and second regions that are not covered by the etch stop layer; and   forming a source electrode and a drain electrode on the semiconductor layer with a space therebetween so that a portion of one of the source electrode and the drain electrode is located over the first region, and a portion of another of the source electrode and the drain electrode is located over the second region.