High speed fpga boot-up through concurrent multi-frame configuration scheme

Abstract

Systems and methods are provided herein for implementing a programmable integrated circuit device that enables high-speed FPGA boot-up through a significant reduction of configuration time. By enabling high-speed FPGA boot-up, the programmable integrated circuit device will be able to accommodate applications that require faster boot-up time than conventional programmable integrated circuit devices are able to accommodate. In order to enable high-speed boot-up, dedicated address registers are implemented for each data line segment of a data line, which in turn significantly reduces configuration random access memory (CRAM) write time (e.g., by a factor of at least two).

1 - 20 . (canceled) 
     
     
         21 . A programmable integrated circuit device, comprising:
 a first data line segment of a plurality of data line segments, wherein the first data line segment comprises:
 a first plurality of configuration random access memory (CRAM) cells; and 
 a first pipeline column coupled to the first plurality of CRAMs, wherein the first pipeline column is configured to:
 receive a plurality of data frames; 
 transmit a first data frame of the plurality of data frames to the first plurality of CRAMs, wherein the first data frame is associated with the first data line segment; and 
 transmit a second data frame of the plurality of data frames to a second data line segment of the plurality of data line segments, wherein the second data frame is associated with the second data line segment, and wherein the second data line segment comprises a second pipeline column coupled to a second plurality of CRAMs. 
 
   
     
     
         22 . The programmable integrated circuit device of  claim 21 , wherein the first data line segment is configured to load the first data frame into the first plurality of CRAMs, and wherein the second data line segment is configured to load the second data frame into the second plurality of CRAMs at a substantially similar time as the loading of the first data frame into the first plurality of CRAMs. 
     
     
         23 . The programmable integrated circuit device of  claim 21 , wherein the first data line segment is coupled to a first address register, and wherein the second data line segment is coupled to a second address register. 
     
     
         24 . The programmable integrated circuit device of  claim 23 , wherein the first data line segment is coupled to the first address register via a first plurality of address lines, wherein the second data line segment is coupled to the second address register via a second plurality of address lines. 
     
     
         25 . The programmable integrated circuit device of  claim 23 , wherein the first data line segment and the second data line segment are configured to load the first data frame and the second data frame, respectively, in response to receiving a respective activation signal at a substantially similar time from the first address register and from the second address register, respectively. 
     
     
         26 . The programmable integrated circuit device of  claim 25 , wherein the respective activation signal is transmitted by the first address register and by the second address register in response to the first data line segment transmitting the first data frame associated to the first plurality of CRAMs and the second data line segment transmitting the second data frame to the second plurality of CRAMs. 
     
     
         27 . The programmable integrated circuit device of  claim 21 , wherein the first pipeline column is configured to receive the plurality of data frames via a plurality of data lines coupled to the first pipeline column. 
     
     
         28 . The programmable integrated circuit device of  claim 21 , wherein the first pipeline column comprises one or more flip flop latches. 
     
     
         29 . The programmable integrated circuit device of  claim 21 , comprising a data register configured to transmit the plurality of data frames to the plurality of data lines. 
     
     
         30 . A method for operating a programmable integrated circuit device, comprising:
 receiving, via a pipeline column of a data line segment, a plurality of data frames;   transmitting, via the pipeline column, a first data frame of the plurality of data frames to a plurality of configuration random access memory (CRAM) cells of the data line segment, wherein the first data frame is associated with the data line segment; and   transmitting, via the pipeline column, a second data frame of the plurality of data frames to an additional plurality of CRAMs of an additional data line segments, wherein the second data frame is associated with the additional data line segment.   
     
     
         31 . The method of  claim 30 , wherein an activation signal is transmitted to the data line segment and the additional data line segment to trigger loading of the first data frame into the data line segment and the second data frame into the second data line segment at a substantially similar time in response to the data line segment and the additional data line segment receiving the first data frame and the second data frame, respectively. 
     
     
         32 . The method of  claim 31 , wherein loading the first data frame into the data line segment comprises loading the first data frame into the plurality of CRAMs, and wherein loading the second data frame into the additional line segment comprises loading the second data frame into the additional plurality of CRAMs. 
     
     
         33 . The method of  claim 30 , wherein receiving the plurality data frames is received via a plurality of data lines associated with the pipeline column. 
     
     
         34 . The method of  claim 30 , wherein transmitting the second data frame comprises pipelining, via the pipeline column, the second data frame to an additional pipeline column of the additional data line segment located downstream of the pipeline column. 
     
     
         35 . A non-transitory machine-readable medium comprising instructions stored thereon for configuring a programmable integrated circuit device, the instructions comprising:
 instructions to receive a plurality of data frames at a pipeline column of a data line segment;   instructions to transmit, via the pipeline column, a first data frame of the plurality of data frames to a plurality of memory cells of the data line segment, wherein the first data frame is associated with the data line segment; and   instructions to transmit, via the pipeline column, a second data frame of the plurality of data frames to an additional pipeline column of an additional data line segment.   
     
     
         36 . The non-transitory machine-readable medium of  claim 35 , wherein the first data frame comprises null data, and wherein the second frame of data comprises null data. 
     
     
         37 . The non-transitory machine-readable medium of  claim 35 , comprising instructions for transmitting an activation signal to the data line segment and to the additional data line segment to trigger loading of the first data frame into the data line segment and the second data frame into the additional data line segment at a substantially similar time in response to the data line segment and the additional data line segment receiving the first data frame and the second data frame, respectively. 
     
     
         38 . The non-transitory machine-readable medium of  claim 37 , wherein loading the first data frame into the data line segment comprises loading the first data frame into the plurality of memory cells, and wherein loading the second data frame into the additional data line segment comprises loading the second data frame into a second plurality of CRAMs of the additional data line segment. 
     
     
         39 . The non-transitory machine-readable medium of  claim 35 , wherein the instructions comprise instructions to:
 scrub data previously loaded into the plurality of memory cells in response to the first data frame being transmitted in the data line segment; and   scrub data previously loaded into an additional plurality of memory cells of the additional data line segment in response to the second data frame being transmitted in the additional data line segment.   
     
     
         40 . The non-transitory machine-readable medium of  claim 35 , wherein instructions to receive the plurality data frames occurs via a plurality of data lines associated with the pipeline column.