Tool-level and hardware-level code optimization and respective hardware modification

Abstract

The present invention related to a method for compiling high-level software code into hardware, transforming each instruction into a respective hardware block and using an execution control signal representing the program pointer for triggering the execution within each respective hardware block.

1 . A method for operating a data processor chip, the method comprising:
 arranging operations having the same timing into groups, wherein arranging the operations includes:
 grouping a sequence of arithmetic instructions into a first group, the arithmetic instructions having a first execution timing; and 
 grouping load instructions into a second group, the load instructions having a second execution timing defined by latency of an access to a memory by the load instructions; 
   processing the sequence of arithmetic instructions using a plurality of arithmetic units of the data processor chip;   processing the load instructions using at least one load unit interfacing to the memory; and   storing operand data and result data for the sequence of arithmetic instructions in a register file.   
     
     
         2 . The method of  claim 1 , wherein the operand data for the sequence of arithmetic instructions is received from the register file and the result data is generated by the sequence of arithmetic instructions and is transmitted to the register file. 
     
     
         3 . The method of  claim 2 , wherein the result data includes result data of instructions within the sequence of arithmetic instructions, wherein the result data of the instructions are forwarded directly as operands data to subsequent instructions within the sequence of arithmetic instructions. 
     
     
         4 . The method of  claim 1 , wherein arranging the operations is performed by a compiler tool compiling high level code into assembly instructions. 
     
     
         5 . The method of  claim 1 , wherein arranging the operations is performed by a hardware unit within the data processor chip. 
     
     
         6 . The method of  claim 1 , wherein the load unit is included in a load-store unit that processes store instructions. 
     
     
         7 . A data processor chip comprising:
 a hardware unit configured to arrange operations having the same timing into groups, wherein the groups include:
 a first group including a sequence of arithmetic instructions having a first execution timing; and 
 a second group including load instructions having a second execution timing defined by latency of an access to a memory by the load instructions; 
   a plurality of arithmetic units configured to process arithmetic instructions;   at least one load unit interfacing to the memory and configured to process the load instructions; and   a register file configured to store operand data and result data for the sequence of arithmetic instructions.   
     
     
         8 . The data processor chip of  claim 7 , wherein the operand data for the sequence of arithmetic instructions is received from the register file and the result data is generated by the sequence of arithmetic instructions and is transmitted to the register file. 
     
     
         9 . The data processor chip of  claim 8 , wherein the result data includes result data of instructions within the sequence of arithmetic instructions, wherein the result data of the instructions are forwarded directly as operands data to subsequent instructions within the sequence of arithmetic instructions.