Processing core having shared front end unit

Abstract

A processor having one or more processing cores is described. Each of the one or more processing cores has front end logic circuitry and a plurality of processing units. The front end logic circuitry is to fetch respective instructions of threads and decode the instructions into respective micro-code and input operand and resultant addresses of the instructions. Each of the plurality of processing units is to be assigned at least one of the threads, is coupled to said front end unit, and has a respective buffer to receive and store microcode of its assigned at least one of the threads. Each of the plurality of processing units also comprises: i) at least one set of functional units corresponding to a complete instruction set offered by the processor, the at least one set of functional units to execute its respective processing unit's received microcode; ii) registers coupled to the at least one set of functional units to store operands and resultants of the received microcode; iii) data fetch circuitry to fetch input operands for the at least one functional units' execution of the received microcode.

What is claimed is: 
     
         1 . A processor having one or more processing cores, each of said one or more processing cores comprising:
 front end logic circuitry to fetch respective instructions of threads and decode said instructions into respective micro-code and input operand and resultant addresses of said instructions;   a plurality of processing units, each of said processing units to be assigned at least one of said threads, each processing unit coupled to said front end unit and having a respective buffer to receive and store microcode of its assigned at least one of said threads, each of said plurality of processing units comprising:
 i) at least one set of functional units corresponding to a complete instruction set offered by said processor, said at least one set of functional units to execute its respective processing unit's received microcode; 
 ii) registers coupled to said at least one set of functional units to store operands and resultants of said received microcode; 
 iii) data fetch circuitry to fetch input operands for said at least one functional units' execution of said received microcode. 
   
     
     
         2 . The processor of  claim 1  wherein said functional units are not coupled to any logic circuitry used to perform out-of-order execution of said received micro-code. 
     
     
         3 . The processor of  claim 2  wherein said processor includes N processing units. 
     
     
         4 . The processor of  claim 1  wherein said functional unit units are not coupled to any logic circuitry to perform speculative execution of said received micro-code. 
     
     
         5 . The processor of  claim 4  wherein said processor includes N processing units. 
     
     
         6 . The processor of  claim 1  wherein said processor does not include circuitry for any of said threads to issue instructions in parallel for any one of said threads. 
     
     
         7 . The processor of  claim 6  wherein said processor includes N processing units. 
     
     
         8 . A method performed by a processor, comprising:
 performing at least one of a) and b) below with same logic circuitry of a processing core of said processor:
 a) fetching first and second instructions of two different threads; 
 b) decoding said first and second instructions into respective units of microcode, input operand address information and resultant address information; 
   dispatching said respective units of microcode and address information to two different processing units; and,   at each processing unit performing the following for its respective one of said two threads:
 storing its respective thread's microcode; 
 fetching input operand data with a received input operand address; 
 executing received microcode upon said fetched input operand with functional unit circuitry that is part of a set of functional units that support a complete general purpose instruction set. 
   
     
     
         9 . The method of  claim 8  where a first of said processing units is a first processing unit and a second of said processing units is an Nth processing unit. 
     
     
         10 . The method of  claim 9  wherein software assigns a first of said threads to said first processing unit and a second of said threads to said Nth processing unit. 
     
     
         11 . The method of  claim 8  wherein both said threads are not processed with any speculative execution logic circuitry. 
     
     
         12 . The method of  claim 8  wherein both said threads are not processed with any out-of-order execution logic circuitry. 
     
     
         13 . The method of  claim 8  wherein both said threads do not issue their respective instructions in parallel. 
     
     
         14 . A processor, comprising:
 at least two processing cores each having:   a front end unit to fetch all respective instructions of all threads processed by its processing core and decode said instructions into respective micro-code and input operand and resultant addresses of said instructions;   said front end unit coupled to all general purpose processing units of its processing core, each of said processing units to be assigned at least one of said threads, each processing unit coupled to said front end unit to receive microcode and input operand and resultant addresses of its assigned at least one of said threads, each of said plurality of processing units comprising:
 i) at least one set of functional units corresponding to a complete general purpose instruction set offered by said processor, said at least one set of functional units to execute its respective processing unit's received microcode; 
 ii) registers coupled to said at least one set of functional units to store operands and resultants of said received microcode; 
 iii) data fetch circuitry to fetch input operands for said at least one functional units' execution of said received microcode; 
   an interconnection network coupled to said plurality of processing units;   a last level cache coupled to said interconnection network.   
     
     
         15 . The processor of  claim 14  wherein said functional units are not coupled to any logic circuitry used to perform out-of-order execution of said received micro-code. 
     
     
         16 . The processor of  claim 15  wherein said processor includes N processing units. 
     
     
         17 . The processor of  claim 14  wherein said functional units are not coupled to any logic circuitry to perform speculative execution of said received micro-code. 
     
     
         18 . The processor of  claim 17  wherein said processor includes N processing units. 
     
     
         19 . The processor of  claim 14  wherein said processor does not include circuitry for any of said threads to issue instructions in parallel for any one of said threads. 
     
     
         20 . The processor of  claim 19  wherein said processor includes N processing units.