Hybrid memory architectures

Abstract

Methods and apparatuses for providing a hybrid memory module having both volatile and non-volatile memories to replace a DDR channel in a processing system.

What is claimed is: 
     
         1 . A system having an integrated circuit (IC) package, the system comprising:
 a processing core disposed within the IC package;   a volatile memory coupled with the processing core via an internal interface within the IC package, the volatile memory to operate as a last-level hardware managed cache memory;   a non-volatile memory coupled with the processing core via the internal interface within the IC package, the non-volatile memory to operate as a disk cache;   a memory interface coupled with the processing core, the memory interface to provide a communication interface to an external memory component.   
     
     
         2 . The system of  claim 1  further comprising a second processing core. 
     
     
         3 . The system of  claim 1  wherein the volatile memory comprises an embedded dynamic random access memory (eDRAM). 
     
     
         4 . The system of  claim 1  wherein the volatile memory comprises a resistive random access memory (resistive-RAM). 
     
     
         5 . The system of  claim 1  wherein the volatile memory comprises a ferroelectric random access memory (ferroelectric-RAM). 
     
     
         6 . The system of  claim 1  wherein the non-volatile memory comprises a phase change memory (PCM). 
     
     
         7 . The system of  claim 1  wherein the non-volatile memory comprises a NAND flash memory. 
     
     
         8 . The system of  claim 1  wherein the memory interface comprises a user-detachable interface to allow a user to selectively connect and disconnect a memory module comprising at least the volatile memory and the non-volatile memory. 
     
     
         9 . The system of  claim 1  further comprising a memory module, the memory module comprising:
 a first user-detachable interface to allow a user to selectively connect and disconnect the volatile memory; and 
 a second user-detachable interface to allow the user to selectively connect and disconnect the non-volatile memory. 
 
     
     
         10 . A method comprising:
 receiving a data request;   searching a cache memory disposed on a die having a processor core generating the data request in response to the data request;   searching a memory module comprising both volatile and non-volatile memory in response to the requested data not being found in the cache memory, wherein the memory module is external to the die having the processor core generating the data request;   searching an external memory in response to the requested data not being found in the memory module, wherein the memory module is external to the die having the processor core generating the data request and the memory module.   
     
     
         11 . The method of  claim 10  wherein the external memory comprises a phase change memory. 
     
     
         12 . The method of  claim 10  wherein the volatile memory comprises an embedded dynamic random access memory (eDRAM). 
     
     
         13 . The method of  claim 10  wherein the volatile memory comprises a resistive random access memory (resistive-RAM). 
     
     
         14 . The method of  claim 10  wherein the volatile memory comprises a ferroelectric random access memory (ferroelectric-RAM). 
     
     
         15 . The method of  claim 10  wherein the non-volatile memory comprises a NAND flash memory. 
     
     
         16 . A processing system having comprising:
 a processing core disposed within a first IC package;   a volatile memory disposed within a second IC package, the volatile memory coupled with the processing core via an interface between the first IC package and the second IC package, the volatile memory to operate as a last-level hardware managed cache memory;   a non-volatile memory disposed within the second IC package, the non-volatile memory coupled with the processing core via the interface between the first IC package and the second IC package, the non-volatile memory to operate as a disk cache;   a memory interface coupled with the processing core, the memory interface to provide a communication interface to an external memory component.   
     
     
         17 . The processing system of  claim 16  further comprising a second processing core. 
     
     
         18 . The processing system of  claim 16  wherein the volatile memory comprises an embedded dynamic random access memory (eDRAM). 
     
     
         19 . The processing system of  claim 16  wherein the volatile memory comprises a resistive random access memory (resistive-RAM). 
     
     
         20 . The processing system of  claim 16  wherein the volatile memory comprises a ferroelectric random access memory (ferroelectric-RAM).