Wafer Level Molded PPGA (Pad Post Grid Array) for Low Cost Package

Abstract

A method to fabricate a land grid array wafer level chip scale package is described. A silicon die is provided. A dielectric layer is deposited on the silicon die. An opening is etched through the dielectric layer to a metal pad on the silicon die. At least one redistribution layer is formed over the dielectric layer and contacting the metal pad. At least one copper post is formed on the at least one redistribution layer and forms a land grid array. The wafer is sawed partially through on scribe lines to form cuts exposing sides of the silicon die. Thereafter, a molding compound is applied over the at least one redistribution layer and in the cuts wherein the molding compound encapsulates top and side surfaces of the silicon die.

What is claimed is: 
     
         1 . A land grid array wafer level chip scale package comprising:
 a silicon die at a bottom of said package;   at least one redistribution layer connected to said silicon die through an opening through a dielectric layer to a metal pad on a top surface of said silicon die;   at least one copper post contacting said at least one redistribution layer and forming a land grid array; and   a molding compound on said redistribution layer encapsulating top and side surfaces of said silicon die.   
     
     
         2 . The package according to  claim 1  wherein said at least one copper post is exposed by said molding compound and further comprising an oxidation preventing layer on said exposed copper post. 
     
     
         3 . The package according to  claim 2  wherein said oxidation preventing layer comprises organic solderability preservatives (OSP), immersion tin (IT), or electroplated gold. 
     
     
         4 . The package according to  claim 1  wherein said molding compound comprises a mold granular epoxy resin material with a fine filler. 
     
     
         5 . The package according to  claim 1  wherein a printed circuit board is mounted onto said package via said copper post. 
     
     
         6 . A method of fabricating a land grid array wafer level chip scale package comprising:
 providing a silicon die;   depositing a dielectric layer on said silicon die;   etching an opening through said dielectric layer to a metal pad on said silicon die;   forming at least one redistribution layer over said dielectric layer and contacting said metal pad;   forming at least one copper post on said at least one redistribution layer forming said land grid array;   cutting said wafer partially through on scribe lines to form cuts exposing sides of said silicon die; and   thereafter applying a molding compound over said at least one redistribution layer and in said cuts wherein said molding compound encapsulates top and side surfaces of said silicon die.   
     
     
         7 . The method according to  claim 6  wherein said applying said molding compound comprises:
 compression molding using a mold granular epoxy resin material with a fine filler; 
 curing; and 
 post-curing said mold material. 
 
     
     
         8 . The method according to  claim 6  further comprising:
 lapping said wafer to expose said at least one copper post; and 
 forming an oxidation preventing layer on exposed said at least one copper post. 
 
     
     
         9 . The method according to  claim 8  wherein said oxidation preventing layer comprises organic solderability preservatives (OSP), immersion tin (IT), or electroplated gold coated, printed, or plated onto said exposed at least one copper post. 
     
     
         10 . The method according to  claim 6  further comprising:
 thinning a backside of said wafer; and 
 thereafter singulating said wafer to form packages. 
 
     
     
         11 . The method according to  claim 10  further comprising laminating a backside protection film onto thinned said backside of said wafer prior to said singulating step. 
     
     
         12 . The method according to  claim 11  wherein said backside protection film comprises epoxy. 
     
     
         13 . The method according to  claim 6  further comprising:
 providing at least one pad on a printed circuit board 
 applying solder paste on said at least one pad; and 
 surface mounting said at least one copper post of said wafer level chip scale package to said at least one pad on said printed circuit board via said solder paste. 
 
     
     
         14 . A method of fabricating a land grid array wafer level chip scale package comprising:
 providing a silicon die;   depositing a dielectric layer on said silicon die;   etching an opening through said dielectric layer to a metal pad on said silicon die;   forming at least one redistribution layer over said dielectric layer and contacting said metal pad;   forming at least one copper post on said at least one redistribution layer forming a land grid array;   cutting said wafer partially through on scribe lines to form cuts exposing sides of said silicon die;   thereafter applying a molding compound over said at least one redistribution layer and in said cuts wherein said molding compound encapsulates top and side surfaces of said silicon die;   thereafter lapping said wafer to expose said at least one copper post; and   forming an oxidation preventing layer on exposed said at least one copper post.   
     
     
         15 . The method according to  claim 14  wherein said applying said molding compound comprises:
 compression molding using a mold granular epoxy resin material with a fine filler; 
 curing; and 
 post-curing said mold material. 
 
     
     
         16 . The method according to  claim 14  wherein said oxidation preventing layer comprises organic solderability preservatives (OSP), immersion tin (IT), or electroplated gold coated, printed, or plated onto said exposed at least one copper post. 
     
     
         17 . The method according to  claim 14  further comprising:
 thinning a backside of said wafer; and 
 thereafter singulating said wafer to form packages. 
 
     
     
         18 . The method according to  claim 17  further comprising laminating a backside protection film onto thinned said backside of said wafer prior to said singulating step. 
     
     
         19 . The method according to  claim 18  wherein said backside protection film comprises epoxy. 
     
     
         20 . The method according to  claim 6  further comprising:
 providing at least one pad on a printed circuit board 
 applying solder paste on said at least one pad; and 
 surface mounting said at least one copper post of said wafer level chip scale package to said at least one pad on said printed circuit board via said solder paste.