Parallel memory systems

Abstract

The invention relates to a multi-core processor memory system, wherein it is provided that the system comprises memory channels between the multi-core processor and the system memory, and that the system comprises at least as many memory channels as processor cores, each memory channel being dedicated to a processor core, and that the memory system relates at run-time dynamically memory blocks dedicatedly to the accessing core, the accessing core having dedicated access to the memory bank via the memory channel.

1 . A memory device comprising:
 a plurality of memory banks, each memory bank associated with a memory bank controller controlling the memory bank; and   a plurality of data transmission channels,   each of the memory bank controllers and each of the plurality of data transmission channels being connected to a switch for flexible interconnecting of the plurality of data transmission channels and the memory bank controllers.   
     
     
         2 . The memory device of  claim 1 , wherein the plurality of data transmission channels transmit data serially. 
     
     
         3 . The memory device of  claim 1 , wherein multiple data transmission channels of the plurality of data transmission channels are dynamically combined to increase a transmission bandwidth. 
     
     
         4 . The memory device of  claim 1 , wherein the memory device is connectable to a multi-core processor. 
     
     
         5 . The memory device of  claim 4 , wherein at least some of the data transmission channels are connectable to different processor cores of the multi-core processor. 
     
     
         6 . The memory device of  claim 1 , wherein the memory device is a module comprising multiple memory chips. 
     
     
         7 . The memory device of  claim 1 , wherein each of the plurality of data transmission channels connects to a dedicated one of the memory banks, allowing independent parallel access to the plurality of memory banks. 
     
     
         8 . The memory device of  claim 1 , wherein one or more serial interfaces, coupled to the plurality of memory banks, are each adapted to transfer multiple bits in parallel over the plurality of data transmission channels.