Magnon spin valve, magnon sensor, magnon field effect transistor, magnon tunnel junction and magnon memory

Abstract

The present disclosure relates to a magnon spin valve device, a magnon sensor, a magnon field effect transistor, a magnon tunnel junction and a magnon memory. A magnon spin valve device may comprise a first ferromagnetic insulation layer, a non-magnetic conductive layer disposed on the first ferromagnetic insulation layer, and a second ferromagnetic insulation layer disposed on the non-magnetic conductive layer.

What is claimed is: 
     
         1 . A magnon spin valve device comprising:
 a first ferromagnetic insulation layer;   a non-magnetic conductive layer disposed on the first ferromagnetic insulation layer; and   a second ferromagnetic insulation layer disposed on the non-magnetic conductive layer.   
     
     
         2 . The magnon spin valve device of  claim 1 , wherein each of the first ferromagnetic insulation layer and the second ferromagnetic insulation layer comprises one or more of the following materials: R 3 Fe 5 O 12 , MFe 2 O 4 , Fe 3 O 4 , BaFe 12 O 19 , SrFe 12 O 19 , and doped compounds thereof, where R is Y, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb or Lu, and M is Mn, Zn, Cu, Ni, Mg or Co, and
 wherein the non-magnetic conductive layer comprises one or more of the following materials: Cu, Ru, Ag, Cr, and Au.   
     
     
         3 . The magnon spin valve device of  claim 1 , wherein the first ferromagnetic insulation layer has a relatively fixed magnetic moment, and the second ferromagnetic insulation layer has a free magnetic moment that is free to change with an external magnetic field. 
     
     
         4 . The magnon spin valve device of  claim 1 , wherein the non-magnetic conductive layer has a thickness smaller than three times of its spin diffusion length. 
     
     
         5 . The magnon spin valve device of  claim 1 , wherein the magnon spin valve device is used as a magnon sensor. 
     
     
         6 . A magnon field effect transistor comprising:
 a first ferromagnetic region, a second ferromagnetic region, and a third ferromagnetic region each formed of a ferromagnetic material, wherein the second ferromagnetic region is formed of a ferromagnetic insulation material;   a first antiferromagnetic region located between the first ferromagnetic region and the second ferromagnetic region, and formed of an antiferromagnetic material;   a second antiferromagnetic region located between the second ferromagnetic region and the third ferromagnetic region, and formed of an antiferromagnetic material; and   a gate covering the second ferromagnetic region.   
     
     
         7 . The magnon field effect transistor of  claim 6 , wherein the ferromagnetic material comprises a ferromagnetic insulation material or a ferromagnetic conductive material, and the antiferromagnetic material comprises an antiferromagnetic insulation material or an antiferromagnetic conductive material. 
     
     
         8 . The magnon field effect transistor of  claim 7 , wherein the ferromagnetic insulation material comprises one or more of the following materials: R 3 Fe 5 O 12 , MFe 2 O 4 , Fe 3 O 4 , BaFe 12 O 19 , SrFe 12 O 19 , and doped compounds thereof, where R is Y, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb or Lu, and M is Mn, Zn, Cu, Ni, Mg or Co,
 wherein the antiferromagnetic insulation material comprises one or more of the following materials: NiO and CoO, and   the antiferromagnetic conductive material comprises one or more of the following materials: IrMn, PtMn, AuMn, PdMn, FeMn, and NiMn.   
     
     
         9 . The magnon field effect transistor of  claim 6 , wherein the first ferromagnetic region, the second ferromagnetic region, and the third ferromagnetic region have magnetic moments parallel to each other. 
     
     
         10 . The magnon field effect transistor of  claim 6 , wherein the magnon field effect transistor is configured as a magnon logic device, the gate is used as a logic input terminal of the magnon logic device, either the first ferromagnetic region or the third ferromagnetic region is used as a logic output terminal of the magnon logic device. 
     
     
         11 . The magnon field effect transistor of  claim 10 , wherein the magnon field effect transistor is configured as a logical “NOT” gate. 
     
     
         12 . A magnon tunnel junction, comprising:
 a first ferromagnetic layer formed of a ferromagnetic material;   a first antiferromagnetic layer located on the first ferromagnetic layer and formed of an antiferromagnetic material; and   a second ferromagnetic layer located on the first antiferromagnetic layer and formed of a ferromagnetic material.   
     
     
         13 . The magnon tunnel junction of  claim 12 , wherein the ferromagnetic material includes a ferromagnetic insulation material or a ferromagnetic conductive material, and
 wherein the antiferromagnetic material comprises an antiferromagnetic insulation material or an antiferromagnetic conductive material.   
     
     
         14 . The magnon tunnel junction of  claim 12 , wherein the first ferromagnetic layer has a fixed magnetic moment, and the second ferromagnetic layer has a free magnetic moment that is free to change with an external magnetic field. 
     
     
         15 . The magnon tunnel junction of  claim 12  further comprises:
 a second antiferromagnetic layer located on the second ferromagnetic layer and formed of an antiferromagnetic material; and 
 a third ferromagnetic layer located on the second antiferromagnetic layer and formed of a ferromagnetic material. 
 
     
     
         16 . The magnon tunnel junction of  claim 15 , wherein the first ferromagnetic layer and the third ferromagnetic layer have magnetic moments parallel to each other, and the second ferromagnetic layer has a free magnetic moment that is free to change with an external magnetic field. 
     
     
         17 . The magnon tunnel junction of  claim 12 , wherein the magnon tunnel junction is configured as a magnon memory cell in a magnon memory device, the magnon memory device comprises a plurality of the magnon memory cell, and each magnon memory cell comprises the magnon tunnel junction.