High Rate Electric Field Driven Nanoelement Assembly on an Insulated Surface

Abstract

A method for high rate assembly of nanoelements into two-dimensional void patterns on a non-conductive substrate surface utilizes an applied electric field to stabilize against forces resulting from pulling the substrate through the surface of a nanoelement suspension. The electric field contours emanating from a conductive layer in the substrate, covered by an insulating layer, are modified by a patterned photoresist layer, resulting in an increased driving force for nanoelements to migrate from a liquid suspension to voids on a patterned substrate having a non-conductive surface. The method can be used for the production of microscale and nanoscale circuits, sensors, and other electronic devices.

That which is claimed is: 
     
         1 . A method for making a patterned substrate for the assembly of nanoelements, the method comprising the steps of:
 (a) depositing a conductive layer on a base layer of nonconducting material;   (b) depositing an insulating layer on the conductive layer;   (c) depositing a patterning layer on the insulating layer; and   (d) removing one or more portions of the patterning layer to create a pattern of voids in the patterning layer, whereby a patterning layer is formed, the patterning layer comprising a pattern of voids, the walls of the voids formed by the patterning layer and the bottom of the voids formed by the insulating layer.   
     
     
         2 . The method of  claim 1 , wherein:
 the insulating and patterning layer are the same;   steps (b) and (c) are combined into one step of deposition to produce a single structure having an upper portion and a lower portion, the lower portion contacting the conductive layer; and   step (d) comprises removing one or more portions of the upper portion of the single structure to create a pattern of voids.   
     
     
         3 . The method of  claim 1 , further comprising:
 depositing an adhesion layer between the base layer and the conductive layer.   
     
     
         4 . The method of  claim 3 , wherein the adhesion layer comprises chromium. 
     
     
         5 . The method of  claim 1 , wherein the base layer comprises a material selected from the group consisting of silicon, silicon dioxide, a metal oxide, sapphire, silicon carbide, a ceramic material, a semiconductor material, and a non-conductive organic polymer. 
     
     
         6 . The method of  claim 5 , wherein the metal oxide is alumina or titania. 
     
     
         7 . The method of  claim 1 , wherein the base layer is formed by a method selected from the group consisting of molding, polymerization, cutting from a block or ingot, polishing, physical deposition, and chemical deposition. 
     
     
         8 . The method of  claim 1 , wherein the conductive layer comprises a metal, a metal alloy, or a conductive polymer. 
     
     
         9 . The method of  claim 8 , wherein the metal is selected from the group consisting of gold, silver, copper, chromium, aluminum, titanium, tungsten, and platinum, and alloys thereof. 
     
     
         10 . The method of  claim 8 , wherein the metal is deposited by chemical vapor deposition, physical vapor deposition, or sputtering. 
     
     
         11 . The method of  claim 8  wherein the conductive layer is a conductive polymer. 
     
     
         12 . The method of  claim 11 , wherein the conductive polymer is deposited by polymerization or electrophoresis. 
     
     
         13 . The method of  claim 8 , wherein the conductive polymer is selected from the group consisting of poly(styrenesulfonate)-poly(2,3-dihydrothieno(3,4-1,4-dioxin), polyacetylene, polydiacetylene, polypyrrole, polyanaline, polythiophene, poly(p-phenylene), polyazulene, and polyquinoline. 
     
     
         14 . The method of  claim 1 , wherein the conductive layer has a thickness in the range of about 40 nm to about 100 nm. 
     
     
         15 . The method of  claim 1 , wherein the insulating layer is silicon dioxide, a dielectric material, or a non-conductive polymer. 
     
     
         16 . The method of  claim 15 , wherein the dielectric material is a glass, a ceramic, or a plastic. 
     
     
         17 . The method of  claim 1 , wherein the insulating layer is deposited by chemical or physical deposition. 
     
     
         18 . The method of  claim 17 , wherein the insulating layer is deposited by plasma enhanced chemical vapor deposition. 
     
     
         19 . The method of  claim 17 , wherein the thickness of the non-conductive layer is in the range of about 50 nm to about 5 μm. 
     
     
         20 . The method of  claim 1 , wherein the patterning layer is a photoresist layer and the removing in step (d) is performed by lithography.