Systems and methods for input/output computing resource control

Abstract

Disclosed herein are systems and methods for isolating input/output computing resources. In some embodiments, a host device may include a processor and logic coupled with the processor, to identify a tag identifier (Tag ID) for a process or container of the host device. The Tag ID may identify a queue pair of a hardware device of the host device for an outbound transaction from the processor to the hardware device, to be conducted by the process or container. Logic may further map the Tag ID to a Process Address Space Identifier (PASID) associated with an inbound transaction from the hardware device to the processor that used the identified queue pair. The process or container may use the PASID to conduct the outbound transaction via the identified queue pair. Other embodiments may be disclosed and/or claimed.

1 - 25 . (canceled) 
     
     
         26 . A computing node, comprising:
 a processor;   logic coupled with the processor, to: identify a queue pair of a hardware device communicatively coupled with the computing node for an outbound transaction from the processor to the hardware device, the outbound transaction to be conducted by the process or container; and map the queue pair to an address space associated with an inbound transaction from the hardware device to the processor, wherein the process or container is to use an identification of the mapped address space to conduct the outbound transaction via the identified queue pair.   
     
     
         27 . The computing node of  claim 26 , wherein the logic is to:
 identify the queue pair as an unused queue pair from a pool of queue pairs;   generate a tag identifier (Tag ID) associated with the identified queue pair; and   cause storage of the Tag ID for the queue pair in a register of the computing node.   
     
     
         28 . The computing node of  claim 27 , wherein the outbound transaction comprises a request to access a memory associated with the hardware device, wherein the logic is to:
 receive the memory access request;   determine whether the memory access request includes the Tag ID; and   based on a result of the determination, provide the Tag ID to second logic.   
     
     
         29 . The computing node of  claim 28 , wherein the Tag ID comprises a namespace identifier associated with the memory request. 
     
     
         30 . The computing node of  claim 29 , wherein the logic is to:
 determine whether the queue pair is enabled with capability to be associated with an address space; and   based on a result of the determination,   include the Tag ID in an address space identification field in a data packet prefix; and   generate a transaction to the queue pair in accordance with the memory request and in association with the data packet prefix, to cause the transaction to be performed by the process or container using the queue pair.   
     
     
         31 . The computing node of  claim 30 , wherein the data packet is a Transaction Layer Packet (TLP) of a Peripheral Component Interconnect Express (PCIe) transaction, and wherein the hardware device is a PCIe device. 
     
     
         32 . The computing node of  claim 30 , wherein the logic is first logic, wherein the computing node further comprises the second logic coupled with the processor to:
 set an address space association enable indicator of a per-queue address space association register of the hardware device to enable the hardware device to perform the transaction using the queue pair;   use the namespace identifier to set the per-queue address space association register; and   re-initialize the queue pair to be used in the transaction.   
     
     
         33 . The computing node of  claim 32 , further comprising third logic coupled with the processor to store address space association information associated with inbound transactions between the hardware device and the processor in a address space association repository, wherein the third logic is to retrieve the address space association information from the address space association repository. 
     
     
         34 . A hardware device, comprising:
 logic to perform privilege check for an outbound transaction initiated by a computing node and associated with an address space that indicates a queue pair of the hardware device, wherein the address space is associated with a process or container of the computing node associated with the outbound transaction, wherein to perform the privilege check includes to compare information about the address space with address space values stored in a per-queue address space association register of the hardware device, and to allow the outbound transaction based at least in part on a result of the comparison.   
     
     
         35 . The hardware device of  claim 34 , wherein the logic is to, prior to the comparison of the address space information associated with the queue pair with address space values stored in the per-queue address space association register:
 determine that a address space association indicator of an address space association register is set; and   determine that an address space association indicator of the per-queue address space association register associated with the queue pair is set,   wherein the address space association capability register provides for enablement of outbound transactions, and wherein the outbound transactions comprise Peripheral Component Interconnect Express (PCIe) transactions, and wherein the hardware device is an input-output (I/O) PCIe device.   
     
     
         36 . The hardware device of  claim 35 , wherein the address space association information is included in a Transaction Layer Packet (TLP) prefix, wherein the address space association capability indicator indicates a capability of the hardware device to perform outbound transactions based on the address space association information in the TLP prefix. 
     
     
         37 . The hardware device of  claim 34 , wherein the logic is to receive the address space association information from the computing node. 
     
     
         38 . A method for utilizing resources of a hardware device communicatively coupled with a computing node, comprising:
 identifying, by the computing node, a queue pair of a hardware device of the computing node for an outbound transaction between the processor and the hardware device, the outbound transaction to be conducted by the process or container; and   mapping, by the computing node, the queue pair to an address space associated with an inbound transaction between the hardware device and the processor, to enable the outbound transaction by the process or container via the identified queue pair.   
     
     
         39 . The method of  claim 38 , further comprising:
 identifying, by the computing node, the queue pair as an unused queue pair from a pool of queue pairs;   generating, by the computing node, a tag identifier (Tag ID) associated with the identified queue pair; and   causing, by the computing node, storage of the Tag ID for the queue pair in a register of the computing node.   
     
     
         40 . The method of  claim 39 , wherein the outbound transaction comprises a request to access a memory associated with the hardware device, wherein the method further comprises:
 receiving, by the computing node, the memory access request; and   determining, by the computing node, whether the memory access request includes the Tag ID, wherein the Tag ID comprises a namespace identifier associated with the memory request.   
     
     
         41 . The method of  claim 40 , further comprising:
 determining, by the computing node, whether the queue pair is enabled to support address space association; and   based on a result of the determination,   including, by the computing node, information about the address space association in a data packet prefix; and   generating, by the computing node, a transaction to the queue pair in accordance with the memory request and in association with the address space association information in the data packet prefix, to perform the transaction using the queue pair.   
     
     
         42 . The method of  claim 41 , further comprising:
 setting, by the computing node, a address space association enabled indicator of a per-queue address space association register of the hardware device to enable the hardware device to perform the transaction using the queue pair;   using, by the computing node, the namespace identifier to set the per-queue address space association register; and   re-initializing, by the computing node, the queue pair to be used in the transaction.   
     
     
         43 . The method of  claim 39 , further comprising:
 retrieving, by the computing node, the address space association information from a address space association repository associated with the computing node.   
     
     
         44 . A method for utilizing resources of a hardware device communicatively coupled with a computing node, comprising:
 comparing, by the hardware device of the computing node, address space association information that indicates a queue pair of the hardware device, with address space values stored in a per-queue address space association register of the hardware device, wherein the address space association information is of a process or container of the computing node associated with an outbound transaction; and   performing or causing to be performed, by the hardware device, the outbound transaction based at least in part on a result of the comparison.   
     
     
         45 . The method of  claim 44 , further comprising:
 prior to the comparison of the address space association information associated with the queue pair with address space values stored in the per-queue address space association register,   determining, by the hardware device, that a address space association capability indicator of a address space association capability register is set; and   determining, by the hardware device, that a address space association enabled indicator of the per-queue address space association register associated with the queue pair is set,   wherein the address space association capability register provides for performance of outbound transactions, wherein the outbound transactions comprise Peripheral Component Interconnect Express (PCIe) transactions, and wherein the hardware device is a PCIe device.   
     
     
         46 . The method of  claim 45 , further comprising:
 receiving, by the hardware device, the address space association information from the computing node.   
     
     
         47 . The method of  claim 44 , wherein the address space association information is included in a Transaction Layer Packet (TLP) prefix. 
     
     
         48 . The method of  claim 47 , wherein the address space association capability indicator indicates a capability of the hardware device to perform outbound transactions based on the address space association information in the TLP prefix. 
     
     
         49 . One or more computer readable media having instructions thereon that, in response to execution by one or more processing devices of an apparatus, cause the apparatus to perform the method of  claim 38 . 
     
     
         50 . One or more computer readable media having instructions thereon that, in response to execution by one or more processing devices of an apparatus, cause the apparatus to perform the method of  claim 44 .