Dynamic re-allocation of signal lanes

Abstract

A computer-implemented method determines that a link operation associated with a first link, among the set of interface links in a computing system, has resulted in a first set of signal lanes, included in the first link, becoming unused. The method further includes determining a link configuration and selecting, based on the link configuration, a second link from among the interface links, and determining a second set of signal lanes, from among the unused signal lanes included in the first link, to include in the second link. The signal lanes to include in the second link are based on an attribute associated with the second link. The method further includes dynamically reconfiguring the signal lanes included in the second to set to be included in the lanes in the second link. Some computing systems include a lane routing device connected to signal lanes of links among the interface links.

What is claimed is: 
     
         1 . A computer-implemented method comprising:
 detecting a link operation applied to a first link among a plurality of interface links;   in response to detecting the link operation, determining a link configuration associated with the plurality of interface links, the link configuration including a first set of signal lanes included in the first link that are unused and a respective physical location of the plurality of links within a computer;   selecting a second link among the plurality of interface links based on the physical location of the second link within the computer as compared to the physical location of other links of the plurality of interface links;   determining, based at least in part on a link attribute associated with the second link, a second set of signal lanes, the second set of signal lanes comprising signal lanes among the first set of signal lanes; and   dynamically re-configuring the signal lanes among the second set of signal lanes to be included in the second link.   
     
     
         2 . The method of  claim 1  further comprising:
 determining that the second set of signal lanes comprises fewer than all of the signal lanes in the first set of signal lanes; 
 selecting, based at least in part on the link configuration, a third link among the plurality of interface links; 
 determining, based at least in part on a link attribute associated with the third link, a third set of signal lanes, the third set comprising signal lanes among the first set of signal lanes not included in the second set of signal lanes; and 
 dynamically re-configuring the signal lanes among the third set of signal lanes to be included in the third link. 
 
     
     
         3 . The method of  claim 1 , wherein detecting the link operation comprises detecting one of a program interrupt or a status bit in a hardware register from hardware associated with the first link. 
     
     
         4 . The method of  claim 1 , wherein detecting the link operation comprises detect the periodically polling a status of a device connected to the first link. 
     
     
         5 . The method of  claim 1 , wherein selecting the second link based on the physical location of the second link within the computer comprises selecting the second link based on the second link having a shorter hardware path length within the computer between a device connected to the second link and a processor, as compared to the other links of the plurality of interface links. 
     
     
         6 . The method of  claim 1 , wherein the link attribute comprises a number of signal lanes included in the second link, and wherein determining the second set of signal lanes comprises determining to include in the second link a number of signal lanes among the first set of signal lanes that increases the number of signal lanes included in the second link to a number of signal lanes corresponding to an allowable link width. 
     
     
         7 . The method of  claim 1 , wherein the link attribute comprises a number of signal lanes that can be utilized by a device connected to the second link, and wherein determining the second set of signal lanes comprises determining to include in the second link a number of signal lanes among the first set of signal lanes that increases the number of signal lanes included in the second link to a number of signal lanes that can be utilized by the device. 
     
     
         8 . A computing system comprising:
 a lane routing device;   a plurality of interface links;   a first link among the plurality of interface links, wherein the first link comprises first signal lanes connected to the lane routing device;   a second link among the plurality of interface links, wherein the second link comprises second signal lanes connected to the lane routing device; and   at least one processor, wherein the at least one processor is configured to:   detect a link operation applied to the first link;   in response to detecting the link operation, determine a link configuration associated with the plurality of interface links, the link configuration including a first set of signal lanes included in the first link that are unused as a result of the detected link operation and a respective physical location of the plurality of links;   select the second link among the plurality of interface links based on the physical location of the second link as compared to the physical location of other links of the plurality of interface links;   determine, based at least in part on a link attribute associated with the second link, a second set of signal lanes, the second set of signal lanes comprising signal lanes among the first set of signal lanes; and   direct the lane routing device to dynamically re-configure the signal lanes among the second set of signal lanes to be included in the second link.   
     
     
         9 . The system of  claim 8 , wherein the system further comprises a third link among the plurality of interface links, wherein the third link comprises third signal lanes connected to the lane routing device, and wherein the at least one processor is further configured to:
 determine that the second set of signal lanes comprises fewer than all of the signal lanes included in the first set of signal lanes;   select, based at least in part on the link configuration, the third link;   determine, based at least in part on a link attribute associated with the third link, a third set of signal lanes, the third set comprising signal lanes among the first set of signal lanes not included in the second set of signal lanes; and   dynamically re-configure, using the lane routing device, the signal lanes included in the third set of signal lanes to be included in the third link.   
     
     
         10 . The system of  claim 8 , wherein the at least one processor is configured to detect the link operation by detecting one of a program interrupt or a status bit in a hardware register from hardware associated with the first link. 
     
     
         11 . The system of  claim 8 , wherein the at least one processor is configured to detect the link operation by periodically polling a status of a device connected to the first link. 
     
     
         12 . The system of  claim 8 , wherein the at least one processor is configured to select the second link based on the second link having a shorter hardware path length between a device connected to the second link and the at least one processor, as compared to the other links of the plurality of interface links. 
     
     
         13 . The system of  claim 8 , wherein the link attribute comprises a number of signal lanes included in the second link, and wherein the at least one processor is further configured to include, in the second link, a number of signal lanes among the first set of signal lanes that increases the number of signal lanes included in the second link to a number of signal lanes corresponding to an allowable link width. 
     
     
         14 . The system of  claim 8 , wherein the link attribute comprises a number of signal lanes that can be utilized by a device connected to the second link, and wherein the at least one processor is further configured to include, in the second link, a number of signal lanes among the first set of signal lanes that increases the number of signal lanes included in the second link to a number of signal lanes that can be utilized by the device. 
     
     
         15 . A computer program product for dynamically re-configuring signal lanes, the computer program product comprising a non-transitory computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to:
 detect a link operation applied to a first link among a plurality of interface links;   in response to detecting the link operation, determine a link configuration associated with the plurality of interface links, the link configuration including a first set of signal lanes included in the first link that are unused and a respective physical location of the plurality of links within a computer;   select a second link among the plurality of interface links based on the physical location of the second link within the computer as compared to the physical location of other links of the plurality of interface links;   determine, based at least in part on a link attribute associated with the second link, a second set of signal lanes, the second set of signal lanes comprising signal lanes among the first set of signal lanes; and   dynamically re-configure the signal lanes among the second set of signal lanes to be included in the second link.   
     
     
         16 . The computer program product of  claim 15 , wherein the program instructions further include program instructions to further cause the processor to:
 determine that the second set of signal lanes comprises fewer than all of the signal lanes included in the first set of signal lanes;   select, based at least in part on the link configuration, a third link among the plurality of interface links;   determine, based at least in part on a link attribute associated with the third link, a third set of signal lanes, the third set comprising signal lanes among the first set of signal lanes not included in the second set of signal lanes; and   dynamically re-configure the signal lanes included in the third set of signal lanes to be included in the third link.   
     
     
         17 . The computer program product of  claim 15 , wherein the program instructions further include program instructions to further cause the processor to detect the link operation by detecting one of a program interrupt or a status bit in a hardware register from hardware associated with the first link. 
     
     
         18 . The computer program product of  claim 15 , wherein the program instructions further include program instructions to further cause the processor to detect the link operation by periodically polling a status of a device connected to the first link. 
     
     
         19 . The computer program product of  claim 15 , wherein the program instructions further include program instructions to further cause the processor to select the second link based on the second link having a shorter hardware path length within the computer between a device connected to the second link and the processor, as compared to the other links of the plurality of interface links. 
     
     
         20 . The computer program product of  claim 15 , wherein the link attribute comprises at least one of a number of signal lanes included in the second link and a number of a signal lanes that can be utilized by a device connected to the second link, and wherein the program instructions cause the processor to include in the second set of signal lanes a number of signal lanes among the first set of signal lanes that increases the number of signal lanes included in the second link to one of the number of signal lanes corresponding to an allowable link width and the number of signal lanes that can be utilized by the device.