Tooling for coupling multiple electronic chips

Abstract

A method for use with multiple chips, each respectively having a bonding surface including electrical contacts and a surface on a side opposite the bonding surface involves bringing a hardenable material located on a body into contact with the multiple chips, hardening the hardenable material so as to constrain at least a portion of each of the multiple chips, moving the multiple chips from a first location to a second location, applying a force to the body such that the hardened, hardenable material will uniformly transfer a vertical force, applied to the body, to the chips so as to bring, under pressure, a bonding surface of each individual chip into contact with a bonding surface of an element to which the individual chips will be bonded, at the second location, without causing damage to the individual chips, element, or bonding surface.

What is claimed: 
     
         1 . A method comprising:
 forming multiple devices on a first wafer during a front-end process;   forming at least one layer of metal traces on a second wafer during a back-end process, wherein the metal traces are arranged to connect at least two of the multiple devices; and   bonding the first wafer and the second wafer to connect the at least two of the multiple devices on the first wafer by at least one layer of the layers of metal traces on the second wafer.   
     
     
         2 . The method of  claim 1 , further comprising during the front-end process, patterning of implanted dopants in the first wafer. 
     
     
         3 . The method of  claim 1 , further comprising during the back-end process, interconnecting the at least two of the multiple devices by etching vias in an insulating material and depositing a conductive material in the vias. 
     
     
         4 . The method of  claim 1 , wherein forming multiple devices on the first wafer and forming layers of metal traces on the second wafer are done concurrently. 
     
     
         5 . The method of  claim 1 , further comprising forming complementary connection points on the first wafer and the second wafer. 
     
     
         6 . The method of  claim 5 , wherein the complementary connection points on the first wafer and the second wafer are joined together using a tack and fuse approach. 
     
     
         7 . The method of  claim 1 , wherein forming multiple devices on the first wafer and forming layers of metal traces on the second wafer are in parallel. 
     
     
         8 . An apparatus having programmed instructions to:
 form multiple devices on a first wafer during a front-end process;   form at least one layer of metal traces on a second wafer during a back-end process, wherein the metal traces are arranged to connect at least two of the multiple devices; and   couple the first wafer and the second wafer to connect the at least two of the multiple devices on the first wafer by at least one layer of the layers of metal traces on the second wafer.   
     
     
         9 . The apparatus of  claim 8 , wherein forming multiple devices on the first wafer and forming layers of metal traces on the second wafer are done concurrently. 
     
     
         10 . The apparatus of  claim 8 , wherein the apparatus is further programmed to form complementary connection points on the first wafer and the second wafer. 
     
     
         11 . The apparatus of  claim 10 , wherein the apparatus is further programmed to thin the first wafer. 
     
     
         12 . The apparatus of  claim 8 , wherein the first wafer and the second wafer are coupled together using a remote attach approach. 
     
     
         13 . The apparatus of  claim 8 , wherein the front-end process and the back-end process use different formation processes. 
     
     
         14 . The apparatus of  claim 13 , wherein the different formation processes are independent of chip design rules. 
     
     
         15 . A dual-process method comprising:
 a front-end process forming a plurality of devices on a first wafer;   a back-end process forming at least one layer of metal trace on a second wafer, wherein the at least one layer is arranged to connect at least two of the plurality of devices; and   connecting the at least two multiple devices on the first waver by the at least one layer of metal trace on the second wafer.   
     
     
         16 . The dual-process method of  claim 15 , wherein the back-end process further includes interconnecting the at least two of the multiple devices by etching vias in an insulating material and depositing a conductive material in the vias. 
     
     
         17 . The dual-process method of  claim 15 , wherein the front-end process and the back-end process are done concurrently. 
     
     
         18 . The dual-process method of  claim 15 , wherein during both the front-end process and the back-end process, forming complementary connection points on the first wafer and the second wafer. 
     
     
         19 . The dual-process method of  claim 18 , wherein the complementary connection points on the first wafer and the second wafer are joined together using a tack and fuse approach. 
     
     
         20 . The dual-process method of  claim 15 , wherein the front-end process and the back-end process use different formation processes.