Transistor and its method of manufacture

Abstract

A transistor is disclosed, comprising: a layer of semiconductor material comprising a first portion, a second portion, and a third portion connecting the first portion to the second portion and providing a semiconductive channel between the first portion and the second portion; a conductive first terminal covering and in electrical contact with said first portion of the layer of semiconductor material; a conductive second terminal covering and in electrical contact with said second portion of the layer of semiconductor material; a conductive gate terminal comprising a first overlapping portion covering at least part of the first terminal, and a channel portion covering the third portion of the layer of semiconductor material; and a layer of a first dielectric material, having a first dielectric constant, arranged between the first overlapping portion and the first terminal, and between the channel portion of the gate terminal and the third portion of the layer of semiconductor material. The transistor further comprises a layer of a second dielectric material having a second dielectric constant, the second dielectric constant being lower than the first dielectric constant, the layer of second dielectric material being arranged between at least part of the first overlapping portion and the first terminal, whereby at least part of the first overlapping portion of the gate terminal is separated from the first terminal by the layer of first dielectric material and the layer of second dielectric material.

1 . A transistor comprising:
 a layer (or other body) of semiconductor material comprising a first portion, a second portion, and a third portion connecting the first portion to the second portion and providing a semiconductive channel between the first portion and the second portion;   a conductive first terminal covering and in electrical contact with said first portion of the layer of semiconductor material;   a conductive second terminal covering and in electrical contact with said second portion of the layer of semiconductor material;   a conductive gate terminal comprising a first overlapping portion covering at least part of the first terminal, and a channel portion covering the third portion of the layer of semiconductor material; and   a layer (or other body) of a first dielectric material, having a first dielectric constant, arranged between the first overlapping portion and the first terminal, and between the channel portion of the gate terminal and the third portion of the layer of semiconductor material,   characterised in that the transistor further comprises a layer (or other body) of a second dielectric material having a second dielectric constant, said second dielectric constant being lower than said first dielectric constant, said layer of said second dielectric material being arranged between at least part of the first overlapping portion and the first terminal,   whereby said at least part of the first overlapping portion of the gate terminal is separated from the first terminal by said layer of first dielectric material and said layer of second dielectric material.   
     
     
         2 . A transistor in accordance with  claim 1 , wherein said layer (or other body) of said second dielectric material is arranged to separate all of the first overlapping portion of the gate terminal from the first terminal. 
     
     
         3 . A transistor in accordance with any preceding claim, wherein said layer (or other body) of said second dielectric material is arranged to cover a portion of the first terminal. 
     
     
         4 . A transistor in accordance with  claim 3 , wherein said layer (or other body) of said second dielectric material is arranged to cover all of the first terminal. 
     
     
         5 . A transistor in accordance with any preceding claim wherein said layer (or other body) of said second dielectric material is arranged in contact with the first terminal. 
     
     
         6 . A transistor in accordance with any preceding claim, wherein the gate terminal comprises a second overlapping portion covering at least part of the second terminal, and said layer of first dielectric material is further arranged between the second overlapping portion and said second terminal. 
     
     
         7 . A transistor in accordance with  claim 6 , wherein said layer (or other body) of said second dielectric material is further arranged between at least part of the second overlapping portion and the second terminal, whereby said at least part of the second overlapping portion of the gate terminal is separated from the second terminal by said layer of first dielectric material and said layer of second dielectric material. 
     
     
         8 . A transistor in accordance with  claim 6 , further comprising a further layer (or other body) of said second dielectric material, wherein said further layer of said second dielectric material is arranged between at least part of the second overlapping portion and the second terminal, whereby said at least part of the second overlapping portion of the gate terminal is separated from the second terminal by said layer of first dielectric material and said further layer of second dielectric material. 
     
     
         9 . A transistor in accordance with  claim 7  or  claim 8 , wherein said layer or further layer of said second dielectric material is arranged to separate all of the second overlapping portion of the gate terminal from the second terminal. 
     
     
         10 . A transistor in accordance with any one of  claims 7  to  9 , wherein said layer or further layer of said second dielectric material is arranged to cover a portion of the second terminal. 
     
     
         11 . A transistor in accordance with any one of  claims 7  to  9 , wherein said layer or further layer of said second dielectric material is arranged to cover all of the second terminal. 
     
     
         12 . A transistor in accordance with any one of  claims 7  to  11 , wherein said layer or further layer of said second dielectric material is arranged in contact with the second terminal. 
     
     
         13 . A transistor in accordance with any preceding claim, wherein said layer of said second dielectric material does not overlap said third portion of the layer of semiconductor material. 
     
     
         14 . A transistor in accordance with any one of  claims 8  to  12 , wherein said further layer of said second dielectric material does not overlap said third portion of the layer of semiconductor material. 
     
     
         15 . A transistor in accordance with any preceding claim, wherein the first terminal is one of a source terminal and a drain terminal, and the second terminal is the other one of a source terminal and a drain terminal. 
     
     
         16 . A transistor in accordance with any preceding claim, wherein said second dielectric material is one of: benzocyclobutene, polyimide, parylene, organic silicate polymer. 
     
     
         17 . A method of manufacturing a transistor comprising a layer (or other body) of semiconductor material comprising a first portion, a second portion, and a third portion connecting the first portion to the second portion and providing a semiconductive channel between the first portion and the second portion, the method comprising:
 forming said layer (or other body) of semiconductor material;   forming a layer (or other body) of conductive material over (covering) said layer of semiconductor material;   forming a layer (or other body) of a second dielectric material, having a second dielectric constant, over the layer of conductive material;   patterning the layers of conductive material and second dielectric material to expose said third portion of the layer of semiconductor material, leave a first portion of the layer of conductive material covering the first portion of the layer of semiconductor material, leave a first portion of the layer of second dielectric material covering at least part of the first portion of the layer of conductive material, leave a second portion of the layer of conductive material covering the second portion of the layer of semiconductor material, and leave a second portion of the layer of second dielectric material covering at least part of the second portion of the layer of conductive material, the first and second portions of the layer of conductive material providing a source terminal and a drain terminal respectively;   forming a layer (or other body) of a first dielectric material, having a first dielectric constant, over the first and second portions of the layer of second dielectric material and over the exposed third portion of the layer of semiconductor material, said second dielectric constant being lower than said first dielectric constant; and   forming a further layer (or other body) of conductive material over at least a portion of the layer of first dielectric material covering said third portion of the layer of semiconductor material to provide a gate terminal to which a potential may be applied to control a conductivity of the semiconductive channel.   
     
     
         18 . A method in accordance with  claim 17 , wherein said patterning of the layers of conductive material and second dielectric material comprises using a first mask. 
     
     
         19 . A method in accordance with  claim 17  or  claim 18 , wherein said further layer of conductive material comprises at least one overlapping portion covering at least part of at least one of the source and drain terminals. 
     
     
         20 . A method in accordance with  claim 19 , wherein the further layer of conductive material comprises a first overlapping portion covering at least part of one of the source and drain terminals, and a second overlapping portion covering at least part of the other one of the source and drain terminals. 
     
     
         21 . A method in accordance with any one of  claims 17  to  20 , wherein the further layer of conductive material covers the first, second, and third portions of the layer of semiconductor material. 
     
     
         22 . A method in accordance with any one of  claims 17  to  21 , further comprising patterning the further layer of conductive material. 
     
     
         23 . A method in accordance with  claim 22 , wherein said patterning of the further layer of conductive material comprises using a second mask. 
     
     
         24 . A method in accordance with any one of  claims 17  to  21 , wherein said forming of the further layer of conductive material comprises printing the further layer of conductive material. 
     
     
         25 . A method in accordance with any one of  claims 17  to  24 , wherein said layer of conductor material further comprises a further portion extending from one of the first and second portions of the layer of conductor material. 
     
     
         26 . A method in accordance with  claim 25 , wherein said layer of a second dielectric material comprises a further portion covering said further portion of the layer of conductive material, said layer of a first dielectric material comprises a further portion covering said further portion of the layer of a second dielectric material, and the method further comprises:
 patterning the layers of first dielectric material and second dielectric material to expose at least part of the further portion of the layer of conductive material.   
     
     
         27 . A method in accordance with  claim 26 , wherein said further layer of conductive material comprises a further portion in contact with said at least part of the further portion of the layer of conductive material. 
     
     
         28 . A transistor in accordance with any one of  claims 1  to  16 , further comprising at least one support layer (or other body) arranged to support the layer of semiconductor material. 
     
     
         29 . A transistor in accordance with  claim 28 , wherein said at least one support layer (or other body) comprises at least one of: an insulator; a barrier; a substrate; and a carrier. 
     
     
         30 . A method in accordance with any one of  claims 17  to  27 , further comprising providing at least one support layer (or other body) to support the layer of semiconductor material. 
     
     
         31 . A transistor, or method of manufacturing a transistor, substantially as hereinbefore described with reference to the accompanying drawings.