Test systems and methods for chips in wafer scale photonic systems

Abstract

A qualification apparatus for a photonic chip on a wafer that leaves undisturbed an edge coupler that provides an operating port for the photonic devices or circuits on the chip during normal operation in order to not introduce extra loss in the optical path of the final circuit. The qualification apparatus provides an optical path that is angled with regard to the surface of the chip, for example by using a grating coupler. The qualification apparatus can be removed after the chip is qualified. Optionally, the qualification apparatus can be left in communication with the chip and optionally employed as an input port for the chip after the chip has been separated from other chips on a common substrate.

1 - 16 . (canceled) 
     
     
         17 . A wafer comprising:
 a plurality of photonic chips defined in or upon the wafer, the plurality of photonic chips including at least one photonic chip comprising:
 a photonic integrated circuit (PIC); 
 an operating port configured to be used during normal operation of the at least one photonic chip after a separation thereof from the wafer; 
 a test port configured for testing the PIC prior to the separation from the wafer; 
 a first optical waveguide connecting the operating port to the PIC; and, 
 a device disposed to couple test light from the test port into the first optical waveguide to be guided into the PIC. 
   
     
     
         18 . The wafer of  claim 17  comprising wherein the at least one photonic chip is separated from another photonic chip defined in or upon the wafer by a dicing line, and wherein the operating port comprises an edge port disposed at the dicing line. 
     
     
         19 . The wafer of  claim 17  wherein the test port comprises a grating coupler configured to receive the test light that propagates at an angle to a free surface of the wafer. 
     
     
         20 . The wafer of  claim 17  further comprising a second optical waveguide connecting the test port to the directional coupler. 
     
     
         21 . The wafer of  claim 20  wherein the test port is configured to couple the test light that propagates at an angle to a free surface of the wafer into the second optical waveguide. 
     
     
         22 . The wafer of  claim 17  comprising a semiconductor material. 
     
     
         23 . The wafer of  claim 17  comprising silicon on insulator. 
     
     
         24 . The wafer of  claim 17  wherein the device comprises a directional coupler.