Allocating and configuring persistent memory

Abstract

Methods and apparatus to allocating and/or configuring persistent memory are described. In an embodiment, memory controller logic configures non-volatile memory into a plurality of partitions at least in part based on one or more attributes. One or more volumes (visible to an application or operating system) are formed from one or more of the plurality of partitions. Each of the one or more volumes includes one or more of the plurality of partitions having at least one similar attribute from the one or more attributes. In another embodiment, memory controller logic configures a Non-Volatile Memory (NVM) Dual Inline Memory Module (DIMM) into a persistent region and a volatile region. Other embodiments are also disclosed and claimed.

1 . One or more non-transitory computer-readable media comprising one or more instructions that when executed on a processor configure the processor to perform one or more operations to:
 cause configuration of a Non-Volatile Dual Inline Memory Module (NVDIMM) device into a plurality of partitions;   cause the NVDIMM device to be byte addressable by an application;   wherein the application is capable of direct access to the NVDIMM device via load/store instructions.   
     
     
         2 . The one or more computer-readable media of  claim 1 , further comprising one or more instructions that when executed on the at least one processor configure the at least one processor to perform one or more operations to cause the application to directly access the NVDIMM device and bypass one or more drivers. 
     
     
         3 . The one or more computer-readable media of  claim 1 , further comprising one or more instructions that when executed on the at least one processor configure the at least one processor to perform one or more operations to allow access to data interleaved across a plurality of NVDIMM devices. 
     
     
         4 . The one or more computer-readable media of  claim 1 , further comprising one or more instructions that when executed on the at least one processor configure the at least one processor to perform one or more operations to cause configuration of the NVDIMM device to be mapped into an address space of the processor. 
     
     
         5 . The one or more computer-readable media of  claim 1 , further comprising one or more instructions that when executed on the at least one processor configure the at least one processor to perform one or more operations to cause a Basic Input/Output System (BIOS) to perform the configuration of the NVDIMM device. 
     
     
         6 . The one or more computer-readable media of  claim 1 , further comprising one or more instructions that when executed on the at least one processor configure the at least one processor to perform one or more operations to cause configuration of the NVDIMM device in accordance with a Reliability, Availability, and Serviceability (RAS) mode. 
     
     
         7 . The one or more computer-readable media of  claim 1 , further comprising one or more instructions that when executed on the at least one processor configure the at least one processor to perform one or more operations to cause configuration of the NVDIMM device at least in part based on information from an Advanced Configuration and Power Interface (ACPI). 
     
     
         8 . The one or more computer-readable media of  claim 1 , further comprising one or more instructions that when executed on the at least one processor configure the at least one processor to perform one or more operations to cause a BIOS to store a current version of configuration information for the NVDIMM device. 
     
     
         9 . The one or more computer-readable media of  claim 1 , further comprising one or more instructions that when executed on the at least one processor configure the at least one processor to perform one or more operations to cause a BIOS to perform an initial configuration of the NVDIMM device in accordance with an address map of the processor. 
     
     
         10 . The one or more computer-readable media of  claim 1 , wherein the NVDIMM device comprises one or more of: nanowire memory, Ferro-electric transistor random access memory (FeTRAM), magnetoresistive random access memory (MRAM), Spin Torque Transfer Random Access Memory (STTRAM), byte addressable 3-Dimentional Cross Point Memory, and Phase Change Memory (PCM). 
     
     
         11 . An apparatus comprising:
 logic circuitry to cause configuration of a Non-Volatile Dual Inline Memory Module (NVDIMM) device into a plurality of partitions;   logic circuitry to cause the NVDIMM device to be byte addressable by an application;   wherein the application is capable of direct access to the NVDIMM device via load/store instructions.   
     
     
         12 . The apparatus of  claim 11 , further comprising logic circuitry to cause the application to directly access the NVDIMM device and bypass one or more drivers. 
     
     
         13 . The apparatus of  claim 11 , further comprising logic circuitry to allow access to data interleaved across a plurality of NVDIMM devices. 
     
     
         14 . The apparatus of  claim 11 , further comprising logic circuitry to cause configuration of the NVDIMM device to be mapped into an address space of the processor. 
     
     
         15 . The apparatus of  claim 11 , further comprising logic circuitry to cause a Basic Input/Output System (BIOS) to perform the configuration of the NVDIMM device. 
     
     
         16 . The apparatus of  claim 11 , further comprising logic circuitry to cause configuration of the NVDIMM device in accordance with a Reliability, Availability, and Serviceability (RAS) mode. 
     
     
         17 . The apparatus of  claim 11 , further comprising logic circuitry to cause configuration of the NVDIMM device at least in part based on information from an Advanced Configuration and Power Interface (ACPI). 
     
     
         18 . A method comprising:
 causing configuration of a Non-Volatile Dual Inline Memory Module (NVDIMM) device into a plurality of partitions;   causing the NVDIMM device to be byte addressable by an application;   wherein the application is capable of direct access to the NVDIMM device via load/store instructions.   
     
     
         19 . The method of  claim 18 , further comprising causing the application to directly access the NVDIMM device and bypass one or more drivers. 
     
     
         20 . The method of  claim 18 , further comprising allowing access to data interleaved across a plurality of NVDIMM devices.