Tool for modular circuitboard design

Abstract

A system for dynamic circuit board design, preferably including a library of modular circuits and a merge tool. A method for merging modular circuitry into a unified electronics module, preferably including: receiving a circuit board layout, the circuit board layout preferably including a set of modular circuits arranged on a virtual carrier board; converting the circuit board layout into a virtual circuit representation; applying transformations to the virtual circuit representation; and generating a unified circuit board design based on the transformed virtual circuit representation.

We claim: 
     
         1 . A method for electronic circuit generation, comprising:
 receiving a first circuit representation comprising a first plurality of electronic component objects;   receiving a second circuit representation comprising a second plurality of electronic component objects; and   generating a unified circuit representation comprising: a first module and a second module; wherein generating the unified circuit representation comprises:
 for each electronic component object of the first plurality of electronic component objects: generating a respective electronic component object of the unified circuit representation, the respective electronic component object associated with the first module; and 
 for each electronic component object of the second plurality of electronic component objects: generating a respective electronic component object of the unified circuit representation, the respective electronic component object associated with the second module. 
   
     
     
         2 . The method of  claim 1 , wherein:
 the first plurality of electronic component objects comprises a first electronic component object and a second electronic component object;   the second plurality of electronic component objects comprises a third electronic component object and a fourth electronic component object;   the unified circuit representation further comprises:
 a fifth electronic component object generated based on the first electronic component object; 
 a sixth electronic component object generated based on the second electronic component object; 
 a seventh electronic component object generated based on the third electronic component object; and 
 an eighth electronic component object generated based on the fourth electronic component object; 
   the first circuit representation further comprises a first electrical conductor object associated with the first and second electronic component objects;   the second circuit representation further comprises a second electrical conductor object associated with the third and fourth electronic component objects; and   generating the unified circuit representation further comprises:
 generating a third electrical conductor object associated with the first module and with the fifth and sixth electronic component objects; and 
 generating a fourth electrical conductor object associated with the second module and with the seventh and eighth electronic component objects. 
   
     
     
         3 . The method of  claim 2 , wherein:
 the first circuit representation further comprises a first ground object electrically connected to the first electronic component object by a fifth electrical conductor object;   the second circuit representation further comprises a second ground object electrically connected to the third electronic component object by a sixth electrical conductor object;   the unified circuit representation further comprises a unified ground object; and   generating the unified circuit representation further comprises generating a set of one or more electrical conductor objects electrically connecting the fifth and seventh electronic component objects to the unified ground object.   
     
     
         4 . The method of  claim 1 , wherein:
 the first circuit representation comprises a first ground plane;   the second circuit representation comprises a second ground plane; and   generating the unified circuit representation further comprises generating a unified ground plane based on the first and second ground planes.   
     
     
         5 . The method of  claim 1 , further comprising generating a monolithic integrated circuit representation based on the unified circuit representation, wherein:
 the first plurality of electronic component objects comprises a first discrete component object, wherein the first discrete component object represents a first sub-circuit comprising a first plurality of circuit elements; and   generating the monolithic integrated circuit representation comprises, based on the first discrete component object, generating a first integrated circuit component object comprising a representation of the first sub-circuit.   
     
     
         6 . The method of  claim 5 , wherein:
 the second plurality of electronic component objects comprises a second discrete component object, wherein the second discrete component object represents a second sub-circuit comprising a second plurality of circuit elements; and   generating the monolithic integrated circuit representation further comprises, based on the second discrete component object, generating a second integrated circuit component object comprising a representation of the second sub-circuit.   
     
     
         7 . The method of  claim 6 , wherein the first discrete component object is a first discrete op-amp component object and the second discrete component object is a second discrete op-amp component object different from the first discrete op-amp component object. 
     
     
         8 . The method of  claim 1 , further comprising generating electronic device fabrication instructions based on the unified circuit representation. 
     
     
         9 . The method of  claim 8 , further comprising fabricating an electronic device based on the electronic device fabrication instructions. 
     
     
         10 . The method of  claim 1 , wherein:
 the first circuit representation is represented in a first proprietary electrical CAD format;   the second circuit representation is represented in a second proprietary electrical CAD format different from the first proprietary electrical CAD format; and   the unified circuit representation is represented in a third format different from the first and second proprietary electrical CAD formats.   
     
     
         11 . method of  claim 10 , wherein generating the unified circuit representation further comprises:
 translating the first circuit representation into the third format; and   translating the second circuit representation into the third format.   
     
     
         12 . The method of  claim 1 , wherein:
 the first circuit representation further comprises a first line object associated with a first routing layer and a first circuit perimeter;   the second circuit representation further comprises a second line object associated with a second routing layer and a second circuit perimeter;   the second circuit representation is associated with a protected module; and   generating the unified circuit representation further comprises:
 deleting the first line object; 
 based on the association of the second circuit representation with the protected module, including the second line object in the unified circuit representation; and 
 based on the association of the second circuit representation with the protected module, generating a structural support object, wherein the structural support object crosses the second line object of the unified circuit representation. 
   
     
     
         13 . A system for electronic circuit generation, comprising:
 a library of modular circuits, comprising:
 a first circuit representation comprising a first plurality of circuit objects; and 
 a second circuit representation comprising a second plurality of circuit objects; and 
   a merge tool comprising a set of transformation modules;   
       wherein:
 the library of modular circuits provides the first and second circuit representations to the merge tool; 
 the merge tool receives the first and second circuit representations from the library of modular circuits; and 
 the set of transformation modules cooperatively generates a unified circuit representation based on the first and second circuit representations, wherein the unified circuit representation comprises:
 a first module comprising, for each circuit object of the first plurality, a respective associated circuit object; and 
 a second module comprising, for each circuit object of the second plurality, a respective associated circuit object. 
 
 
     
     
         14 . The system of  claim 13 , wherein:
 the library of modular circuits further comprises a plurality of auxiliary modules, wherein each auxiliary module of the plurality is associated with a respective auxiliary module metric; and   the set of transformation modules comprises an auxiliary module selection module, wherein the auxiliary module selection module:
 determines a first module requirement and a second module requirement; and 
 selects an auxiliary module from the plurality of auxiliary modules based on the first and second module requirements and the respective auxiliary module metrics. 
   
     
     
         15 . The system of  claim 14 , wherein:
 each auxiliary module of the plurality is a power module;   the first module requirement is a first module power requirement; and   the second module requirement is a second module power requirement.   
     
     
         16 . The system of  claim 14 , wherein:
 each auxiliary module of the plurality is a computation module;   the first module requirement is a first module computation requirement; and   the second module requirement is a second module computation requirement.   
     
     
         17 . The system of  claim 13 , wherein:
 a first circuit object of the first plurality is associated with an electrical property value and a first tolerance requirement; and   a second circuit object of the second plurality is associated with the electrical property value and a second tolerance requirement more restrictive than the first tolerance requirement;   the unified circuit representation comprises:
 a third circuit object associated with the first circuit object; and 
 a fourth circuit object associated with the second circuit object; and 
   the set of transformation modules comprises an optimization module that associates the second tolerance requirement with the third circuit object, based on the fourth circuit object.   
     
     
         18 . The system of  claim 17 , wherein the electrical property value is selected from the group consisting of: a resistance value, a capacitance value, and an inductance value. 
     
     
         19 . The system of  claim 13 , wherein:
 the unified circuit representation is a hierarchical circuit representation;   the unified circuit representation comprises a first module node, wherein each circuit object of the first module is a respective descendant node of the first module node; and   the unified circuit representation comprises a second module node, wherein each circuit object of the second module is a respective descendant node of the second module node.   
     
     
         20 . The system of  claim 13 , wherein:
 the first circuit representation defines a first spatial arrangement;   the second circuit representation defines a second spatial arrangement;   the first module defines a first module spatial arrangement substantially geometrically similar to the first spatial arrangement; and   the second module defines a second module spatial arrangement substantially geometrically similar to the second spatial arrangement.