Logic Compatible Embedded Flash Memory

Abstract

A non-volatile memory combines a data cell and a reference cell. The data cell includes a coupling structure and a transistor stack. The transistor stack is electrically coupled to the coupling structure. The data cell can store data and output a data signal that corresponds to the data. The reference cell includes a transistor stack that has the same structure as that of the data cell and outputs a reference signal. A column circuit is electrically coupled to the data cell and the first reference cell and configured to process the data signal using the reference signal.

What is claimed is: 
     
         1 . A non-volatile memory, comprising:
 a data cell including a coupling structure that stores a data and a first transistor stack that is electrically coupled to the coupling structure, the data cell outputting a data signal that corresponds to the data;   a first reference cell including a second transistor stack that has a same structure as the first transistor stack and generates a first reference signal; and   a column circuit electrically coupled to the data cell and the first reference cell and configured to process the data signal using the first reference signal.   
     
     
         2 . A non-volatile memory as recited in  claim 1 , wherein the coupling structure includes:
 a coupling transistor electrically coupled to a program line for providing a programming signal;
 a write transistor electrically coupled to a write line for providing a write signal, wherein the coupling and write transistors are arranged to form a floating gate node. 
   
     
     
         3 . A non-volatile memory as recited in  claim 2 , wherein the first transistor stack includes at least three transistors arranged in series and the floating gate node is electrically coupled to a gate terminal of one of the at least three transistors. 
     
     
         4 . A non-volatile memory as recited in  claim 3 , wherein the first transistor stack includes:
 a first transistor having a drain terminal electrically coupled to a bit line for carrying the data signal;   a second transistor having a gate terminal electrically coupled to the floating gate node; and   a third transistor having a source terminal that is electrically coupled to a common source line for providing a common source signal and a gate terminal that is electrically coupled to an erase line providing an erase signal.   
     
     
         5 . A non-volatile memory as recited in  claim 1 , wherein the second transistor stack includes:
 a first transistor having a drain terminal electrically coupled to a reference bit line for carrying the first reference signal;   a second transistor having a gate terminal electrically coupled to a reference word line for providing a reference word signal; and   a third transistor having a source terminal that is electrically coupled to a reference common source line for providing a reference common source signal and a gate terminal that is electrically coupled to a reference erase line providing a reference erase signal.   
     
     
         6 . A non-volatile memory as recited in  claim 1 , wherein the column circuit includes:
 a first transistor electrically coupled to the data cell and clamping the data signal;   a first converting circuit that converts the data signal into a data voltage signal;   a second transistor electrically coupled to the first reference cell and clamping the first reference signal;   a second converting circuit that converts the first reference signal into a reference voltage signal; and   an amplifier electrically coupled to the first and second converting circuits and generating a signal based on comparison between the data voltage signal and the reference voltage signal.   
     
     
         7 . A non-volatile memory as recited in  claim 6 , wherein the first converting circuit includes:
 a transistor for having a source terminal coupled to a voltage source and a drain terminal that is electrically coupled to the first transistor via a first line; and   the first line electrically coupled to the amplifier and carrying the data voltage signal.   
     
     
         8 . A non-volatile memory as recited in  claim 6 , wherein the second converting circuit includes:
 a transistor for having a source terminal coupled to a voltage source and a drain terminal that is electrically coupled to the second transistor via a second line; and   the second line electrically coupled to the amplifier and carrying the reference voltage signal.   
     
     
         9 . A non-volatile memory as recited in  claim 1 , further comprising:
 a second reference cell including a third transistor stack that has a same structure as the first transistor stack and generates a second reference signal,   wherein the column circuit is electrically coupled to the second reference cell and configured to process the data signal using the first and second reference signals.   
     
     
         10 . A non-volatile memory as recited in  claim 9 , wherein the third transistor stack includes:
 a first transistor having a drain terminal electrically coupled to a reference bit line for carrying the reference signal;   a second transistor having a gate terminal electrically coupled to a reference word line for providing a reference word signal; and   a third transistor having a source terminal that is electrically coupled to a reference common source line for providing a reference common source signal and a gate terminal that is electrically coupled to a reference erase line providing a reference erase signal.   
     
     
         11 . A non-volatile memory as recited in  claim 10 , wherein the column circuit includes:
 a first transistor electrically coupled to the data cell and clamping the data signal;   a first converting circuit that converts the data signal into a data voltage signal;   a second transistor electrically coupled to the first reference cell and clamping the first reference signal;   a second converting circuit that converts the first reference signal into a first reference voltage signal;   a third transistor electrically coupled to the second reference cell and clamping the second reference signal;   a second converting circuit that converts the second reference signal into a second reference voltage signal;   an amplifier electrically coupled to the first, second and third converting circuits and generating a signal based on comparison between the data voltage signal, the first reference voltage signal and the second reference voltage signal.   
     
     
         12 . A non-volatile memory cell unit circuit of  claim 1 , wherein the first reference cell further includes:
 a coupling transistor electrically coupled to a reference program line for providing a reference programming signal;
 a write transistor electrically coupled to a reference write line for providing a reference write signal, 
   wherein the coupling and write transistors are arranged to form a floating gate node.   
     
     
         13 . A non-volatile memory as recited in  claim 12 , wherein the second transistor stack includes at least three transistors arranged in series and the floating gate node is electrically coupled to a gate terminal of one of the at least three transistors. 
     
     
         14 . A non-volatile memory as recited in  claim 12 , wherein the second transistor stack includes:
 a first transistor having a drain terminal electrically coupled to a reference bit line for carrying the first reference signal;   a second transistor having a gate terminal electrically coupled to the floating gate node; and   a third transistor having a source terminal that is electrically coupled to a reference common source line for providing a reference common source signal and a gate terminal that is electrically coupled to a reference erase line providing a reference erase signal.   
     
     
         15 . A non-volatile memory as recited in  claim 12 , further comprising:
 a second reference cell including:   a coupling transistor electrically coupled to the reference program line;
 a write transistor electrically coupled to the reference write line, wherein the coupling and write transistors are arranged to form a floating gate node; 
   a first transistor having a drain terminal electrically coupled to a reference bit line for carrying a second reference signal;   a second transistor having a gate terminal electrically coupled to the floating gate node; and   a third transistor having a source terminal that is electrically coupled to a reference common source line for providing a reference common source signal and a gate terminal that is electrically coupled to a reference erase line providing a reference erase signal.   
     
     
         16 . A non-volatile memory as recited in  claim 15 , wherein the third transistor stack includes:
 a first transistor having a drain terminal electrically coupled to a reference bit line for carrying the first reference signal;   a second transistor having a gate terminal electrically coupled to a reference word line for providing a reference word signal; and   a third transistor having a source terminal that is electrically coupled to a reference common source line for providing a reference common source signal and a gate terminal that is electrically coupled to a reference erase line providing a reference erase signal.