Systems, methods, and apparatus for memory cells with common source lines

Abstract

A method for operating a memory device includes the steps of providing a first voltage to a first transistor of a first memory cell and a third transistor of a second memory cell, providing a second voltage to a gate of a second transistor of the first memory cell and a gate of a fourth transistor of the second memory cell, and providing a third voltage to a gate of the first transistor of the first memory cell and a gate of the third transistor of the second memory cell. Other embodiments are also described.

What is claimed is: 
     
         1 . A system comprising:
 a processor;   at least one voltage source; and   a memory array;   wherein:
 the processor is configured to provide control signals to the at least one voltage source and the memory array; 
 the at least one voltage source is configured to generate a plurality of voltages, wherein the plurality of voltages comprises at least one voltage of at least 3.5V; and 
 the memory array comprises:
 a first memory cell comprising a first transistor coupled to a second transistor, wherein the first transistor comprises a memory element; and 
 a second memory cell comprising a third transistor coupled to a fourth transistor; 
 wherein, in response to an initiation of a programming operation, the memory array receives at least one of the plurality voltages at each of a drain of the first transistor, a drain of the third transistor, a gate of the second transistor, a gate of the fourth transistor, and a gate of the first transistor, and 
 wherein receiving the voltages results in a change in one or more electrical characteristics of the memory element. 
 
   
     
     
         2 . The system of  claim 1 , wherein the plurality of voltages further comprises at least one voltage of 1V. 
     
     
         3 . The system of  claim 1 , wherein the memory array is part of a flash memory. 
     
     
         4 . The system of  claim 1 , further comprising a control circuitry comprising the at least one voltage source. 
     
     
         5 . The system of  claim 4 , wherein the control circuitry is configured to the plurality of voltages to the memory array.