Mechanism for disaggregated storage class memory over fabric

Abstract

Mechanisms for disaggregated storage class memory over fabric and associated methods, apparatus, and systems. A rack is populated with pooled system drawers including pooled compute drawers and pooled storage class memory (SCM) drawers, also referred to as SCM nodes. Optionally, a pooled memory drawer may include a plurality of SCM nodes. Each SCM node provides access to multiple storage class memory devices. Compute nodes including one or more processors and local storage class memory devices are installed in the pooled compute drawers, and are enabled to be selectively-coupled to access remote storage class memory devices over a low-latency fabric. During a memory access from an initiator node (e.g., a compute node) to a target node including attached disaggregated memory (e.g., an SCM node), a fabric node identifier (ID) corresponding to the target node is identified, and an access request is forwarded to that target node over the low-latency fabric. The memory access request is then serviced on the target node, and corresponding data is returned to the initiator. During compute node composition, the compute nodes are configured to access disaggregated memory resources in the SCM nodes.

1 . (canceled) 
     
     
         2 . A method, comprising:
 composing memory resources in a first memory component for access by a processor, wherein the memory resources includes at least one memory device remote to the processor and the first memory component comprises at least one dynamic random access memory (DRAM) device;   configuring the processor to form a first memory access request corresponding to a memory region associated with the first memory component;   providing address information relating to the first memory access request via a first packet over a switch coupled between the processor and the first memory component;   transmitting the first packet to the first memory component;   at the first memory component, extracting the address information relating to the first memory access request and performing the first memory access of the first memory component corresponding to the first memory access request; and   providing data corresponding to the first memory access from the first memory component to the processor via a second packet sent over the fabric.   
     
     
         3 . The method of  claim 2 , wherein the first memory component comprises a byte addressable memory. 
     
     
         4 . The method of  claim 3 , wherein the byte addressable memory comprises storage class memory (SCM). 
     
     
         5 . The method of  claim 2 , wherein the first memory component comprises at least one dynamic random access memory (DRAM) Dual Inline Memory Module (DIMM). 
     
     
         6 . A system comprising:
 a first memory component, wherein the first memory component comprises at least one dynamic random access memory (DRAM) device;   at least one processor; and   a switch fabric to communicatively couple the first memory component to the at least one processor, wherein:   a processor is to:
 compose memory resources in a first memory component for access by the processor, the memory resources including at least one memory device remote to the processor, 
 provide a first memory access request corresponding to a memory region associated with the first memory component, 
 provide address information relating to the first memory access request; 
 cause transmission of a first packet to the first memory component using a switch, the first packet including at least the address information relating to the first memory access request; and 
 the first memory component is to:
 extract the address information relating to the first memory access request, 
 perform the first memory access corresponding to the first memory access request, and 
 cause transmission of data corresponding to the first memory access to the processor via a second packet over the fabric. 
 
   
     
     
         7 . The system of  claim 6 , comprising a rack, wherein the rack includes the first memory component, the at least one processor, and the switch fabric. 
     
     
         8 . The system of  claim 6 , wherein the processor is to:
 access the data received via the second packet.   
     
     
         9 . The system of  claim 6 , wherein the first memory component comprises a byte addressable memory. 
     
     
         10 . The system of  claim 9 , wherein the byte addressable memory comprises storage class memory (SCM). 
     
     
         11 . The system of  claim 6 , wherein the first memory component comprises at least one dynamic random access memory (DRAM) Dual Inline Memory Module (DIMM). 
     
     
         12 . A memory system comprising:
 a switch fabric interface capable of coupling to a switch fabric and   at least one volatile memory component coupled to the switch fabric interface, wherein the at least one volatile memory component comprises at least one dynamic random access memory (DRAM) device, the at least one volatile memory component to:
 access address information relating to a first memory access request, the address information received in a first packet received through the switch fabric interface; 
 perform the first memory access of a first memory component corresponding to the first memory access request, and 
 cause transmission of data corresponding to the first memory access to a processor via a second packet through the switch fabric interface. 
   
     
     
         13 . The memory system of  claim 12 , further comprising a switch fabric coupled to the switch fabric interface. 
     
     
         14 . The memory system of  claim 12 , wherein the first memory component comprises a byte addressable memory. 
     
     
         15 . The memory system of  claim 14 , wherein the byte addressable memory comprises storage class memory (SCM). 
     
     
         16 . The memory system of  claim 12 , wherein the first memory component comprises at least one dynamic random access memory (DRAM) Dual Inline Memory Module (DIMM). 
     
     
         17 . A processor system comprising:
 a switch fabric interface capable of coupling to a switch fabric and at least one processor, wherein a processor is to
 provide a first memory access request corresponding to a memory region associated with the first memory component, wherein the first memory component comprises dynamic random access memory (DRAM); 
 provide address information relating to the first memory access request; 
 cause formation of a first packet, the first packet including at least the address information relating to the first memory access request, 
 cause transmission of the first packet to the first memory component using a switch, and 
 access data received via a second packet in response to the transmission of the first packet. 
   
     
     
         18 . The processor system of  claim 17 , further comprising a switch fabric coupled to the switch fabric interface and further comprising the first memory component. 
     
     
         19 . The processor system of  claim 17 , wherein the first memory component comprises a byte addressable memory. 
     
     
         20 . The memory system of  claim 19 , wherein the byte addressable memory comprises storage class memory (SCM). 
     
     
         21 . The processor system of  claim 17 , wherein the first memory component comprises at least one dynamic random access memory (DRAM) Dual Inline Memory Module (DIMM). 
     
     
         22 . A computer-readable medium comprising instructions stored thereon, that if executed by at least one processor, causes the at least one processor to:
 provide a first memory access request corresponding to a memory region associated with the first memory component, wherein the first memory component comprises dynamic random access memory (DRAM);   provide address information relating to the first memory access request;   cause formation of a first packet, the first packet including at least the address information relating to the first memory access request,   cause transmission of the first packet to the first memory component using a switch, and   access data received via a second packet in response to the transmission of the first packet.   
     
     
         23 . The computer-readable medium of  claim 22 , wherein the first memory component comprises a byte addressable memory. 
     
     
         24 . The computer-readable medium of  claim 23 , wherein the byte addressable memory comprises storage class memory (SCM). 
     
     
         25 . The computer-readable medium of  claim 22 , wherein the first memory component comprises at least one dynamic random access memory (DRAM) Dual Inline Memory Module (DIMM).