Method of forming drain extended mos transistors for high voltage circuits

Abstract

A device including both drain extended metal-on-semiconductor (DE_MOS) and low-voltage metal-on-semiconductor (LV_MOS) transistors and methods of manufacturing the same are provided. In one embodiment, the method includes implanting ions of a first-type at a first energy level in a drain portion of a first DE_MOS transistor in a DE_MOS region of a substrate to form the first DE_MOS transistor, and implanting ions of the first-type at a second energy level in a LV_MOS region of the substrate adjust a voltage threshold of a first LV_MOS transistor, while concurrently implanting ions of the first-type at the second energy level in the drain portion of the first DE_MOS transistor to form a drain extension of the first DE_MOS transistor. Other embodiments are also provided.

What is claimed is: 
     
         1 . A method comprising:
 implanting ions of a first-type at a first energy level in a drain portion of a drain extended metal-on-semiconductor (DE_MOS) transistor in a DE_MOS region of a substrate to form a first DE_MOS transistor; and   implanting ions of the first-type at a second energy level in a low-voltage metal-on-semiconductor (LV_MOS) region of the substrate to adjust a voltage threshold of a first LV_MOS transistor, while concurrently implanting ions of the first-type at the second energy level in the drain portion of the first DE_MOS transistor to form a drain extension of the first DE_MOS transistor.   
     
     
         2 . The method of  claim 1  wherein implanting ions of the first-type at the first energy level in the drain portion of the first DE_MOS transistor, comprises concurrently implanting ions of the first-type at the first energy level in a high-voltage metal-on-semiconductor (HV_MOS) region of the substrate to adjust a voltage threshold of a first high-voltage metal-on-semiconductor (HV_MOS) transistor in the HV_MOS region. 
     
     
         3 . The method of  claim 2  further comprising implanting ions of a second-type at the first energy level in a drain portion of a second DE_MOS transistor in the DE_MOS region while concurrently implanting ions of the second-type at the first energy level in the HV_MOS region of the substrate to adjust a voltage threshold of a second HV_MOS transistor in the HV_MOS region. 
     
     
         4 . The method of  claim 3  further comprising implanting ions of the second-type at the second energy level in the LV_MOS region of the substrate to adjust a voltage threshold of a second LV_MOS transistor, while concurrently implanting ions of the second-type at the second energy level in the drain portion of the second DE_MOS transistor to form a drain extension of the second DE_MOS transistor. 
     
     
         5 . The method of  claim 4  wherein:
 implanting ions of the second-type at the first energy level in the HV_MOS region of the substrate to adjust a voltage threshold of the second HV_MOS transistor, further comprises concurrently implanting ions of the second-type at the first energy level in the DE_MOS region to form a source portion of the first DE_MOS transistor; and 
 implanting ions of the first-type at the first energy level in the HV_MOS region of the substrate to adjust a voltage threshold of the first HV_MOS transistor, further comprises concurrently implanting ions of the first-type at the first energy level in the DE_MOS region to form a source portion of the second DE_MOS transistor. 
 
     
     
         6 . The method of  claim 5  wherein the second energy level is lower than the first energy level. 
     
     
         7 . The method of  claim 5  further comprising forming sources and drains in the first DE_MOS transistor and the second DE_MOS transistor, the first LV_MOS transistor and the second LV_MOS transistor, and the first HV_MOS transistor and the second HV_MOS transistor. 
     
     
         8 . The method of  claim 1  wherein the DE_MOS formed is in an input/output (I/O) cell of a non-volatile memory (NVM). 
     
     
         9 . The method of  claim 1  wherein the DE_MOS formed is on pitch with a non-volatile memory (NVM) array of a NVM. 
     
     
         10 . The method of  claim 1  further comprising forming a mask over the substrate exposing a part of the drain portion of the first DE_MOS transistor, and implanting ions of the first-type at a third energy level to form a graduated drain extension of the first DE_MOS transistor. 
     
     
         11 . A method comprising:
 forming a first threshold voltage adjust mask over a surface of a substrate to expose a high-voltage metal-on-semiconductor (HV_MOS) transistor in a high-voltage metal-on-semiconductor (HV_MOS) region of the substrate, and to expose a drain portion of a drain extended metal-on-semiconductor (DE_MOS) transistor in a DE_MOS region of the substrate;   implanting ions of a first-type at a first energy level in the drain portion of the DE_MOS transistor, while concurrently implanting ions of the first-type at the first energy level in the HV_MOS transistor to adjust a voltage threshold of the HV_MOS;   forming a second threshold voltage adjust mask over the surface of a substrate to expose a low-voltage metal-on-semiconductor (LV_MOS) transistor in a low-voltage metal-on-semiconductor (LV_MOS) region of the substrate, and to expose the drain portion of the DE_MOS transistor; and   implanting ions of the first-type at a second energy level in the drain portion of the DE_MOS transistor, while concurrently implanting ions of the first-type at the second energy level in the LV_MOS transistor to adjust a voltage threshold of the LV_MOS.   
     
     
         12 . The method of  claim 11  wherein the second energy level is lower than the first energy level. 
     
     
         13 . The method of  claim 11  further comprising forming sources and drains in the DE_MOS transistor the LV_MOS transistor, and HV_MOS transistor. 
     
     
         14 . The method of  claim 11  wherein the DE_MOS formed is in an input/output (I/O) cell of a non-volatile memory (NVM). 
     
     
         15 . The method of  claim 11  wherein the DE_MOS formed is on pitch with a non-volatile memory (NVM) array of a NVM. 
     
     
         16 . The method of  claim 11  further comprising forming a mask over the substrate exposing a part of the drain portion of the DE_MOS transistor, and implanting ions of the first-type at a third energy level to form a graduated drain extension of the DE_MOS transistor. 
     
     
         17 . A method comprising:
 implanting ions of a first-type at a first energy level in a drain portion of a drain extended metal-on-semiconductor (DE_MOS) transistor in a DE_MOS region of a substrate to form a DE_MOS transistor, while concurrently implanting ions of the first-type at the first energy level in a high-voltage metal-on-semiconductor (HV_MOS) region of the substrate to adjust a voltage threshold of a HV_MOS transistor in the HV_MOS region.   
     
     
         18 . The method of  claim 17  further comprising implanting ions of the first-type at a second energy level in a low-voltage metal-on-semiconductor (LV_MOS) region of the substrate to adjust a voltage threshold of a LV_MOS transistor, while concurrently implanting ions of the first-type at the second energy level in the drain portion of the DE_MOS transistor to form a drain extension of the DE_MOS transistor. 
     
     
         19 . The method of  claim 18  wherein the second energy level is lower than the first energy level. 
     
     
         20 . The method of  claim 18  further comprising forming a first gate oxide for the DE_MOS transistor while concurrently forming a second gate oxide for the HV_MOS transistor.