Semiconductor devices

Abstract

A semiconductor device includes a substrate including a recess, the recess being positioned below an isolation region and having a side portion including a plurality of stepped portions, a plurality of gate electrodes spaced apart from each other on the substrate, and stacked in a direction perpendicular to an upper surface of the substrate, a channel structure passing between a first set of the plurality of gate electrodes, and the isolation region passing between a second set of the plurality of gate electrodes, the isolation region extending from the upper surface of the substrate and having an inclined lateral surface.

1 . (canceled) 
     
     
         2 . A semiconductor device comprising:
 a substrate including a recess, the substrate defining the recess to include a first region, a second region and a third region having different widths;   a stack structure including a plurality of gate electrodes and a plurality of mold insulating layers alternately stacked on the substrate;   a common source line passing through the stack structure to contact the substrate at the first region of the recess; and   an insulating spacer between the stack structure and the common source line, the insulating spacer including silicon nitride.   
     
     
         3 . The semiconductor device of  claim 2 , wherein the common source line extends in a direction parallel to an upper surface of the substrate, and the insulating spacer includes a combination of a silicon compound containing oxygen and a silicon compound containing nitrogen. 
     
     
         4 . The semiconductor device of  claim 2 , wherein the substrate defines a side portion of the recess to include a plurality of stepped portions. 
     
     
         5 . The semiconductor device of  claim 2 , wherein a first space between a lateral surface of a lowermost gate electrode of the plurality of gate electrodes and the common source line is different from a second space between a lateral surface of the substrate at the second region of the recess and the common source line, and
 a lower portion of the insulating spacer includes a bent portion formed according to a shape of the recess, and contacts the substrate at the second region and the third region of the recess.   
     
     
         6 . The semiconductor device of  claim 2 , further comprising:
 a peripheral circuit region below the substrate and on a base substrate, the peripheral circuit region including a plurality of transistors and a plurality of wirings, and the peripheral circuit region overlapping the stack structure in a direction perpendicular to an upper surface of the substrate.   
     
     
         7 . The semiconductor device of  claim 2 , wherein the second region is above the first region, the third region is above the second region, and
 a first width of the first region is narrower than a second width of the second region, and the second width of the second region is narrower than a third width of the third region, and   a lateral surface of the third region is coplanar with a lateral surface of a lowermost mold insulating layer of the plurality of mold insulating layers, the lowermost mold insulating layer contacting an upper surface of the substrate.   
     
     
         8 . The semiconductor device of  claim 4 , wherein the recess further includes a fourth region above the third region, the fourth region including one of the plurality of stepped portions, and the fourth region having a fourth width greater than a third width of the third region, and
 the insulating spacer contacting the substrate at the fourth region of the recess.   
     
     
         9 . A semiconductor device comprising:
 a substrate including a recess, the substrate defining the recess to include a first region, a second region and a third region having different widths;   a stack structure including a plurality of gate electrodes and a plurality of mold insulating layers alternately stacked on the substrate;   a common source line passing through the stack structure to contact the substrate at the first region of the recess; and   an insulating spacer between the stack structure and the common source line, the insulating spacer including a silicon compound containing nitrogen.   
     
     
         10 . The semiconductor device of  claim 9 , wherein the common source line extends in a direction parallel to an upper surface of the substrate, and the insulating spacer includes a combination of a silicon compound containing oxygen and the silicon compound containing nitrogen. 
     
     
         11 . The semiconductor device of  claim 9 , wherein the substrate defines a side portion of the recess to include a plurality of stepped portions. 
     
     
         12 . The semiconductor device of  claim 9 , wherein a first space between a lateral surface of a lowermost gate electrode of the plurality of gate electrodes and the common source line is different from a second space between a lateral surface of the substrate at the second region of the recess and the common source line, and
 a lower portion of the insulating spacer includes a bent portion formed according to a shape of the recess, and contacts the substrate at the second region and the third region of the recess.   
     
     
         13 . The semiconductor device of  claim 9 , further comprising:
 a peripheral circuit region below the substrate and on a base substrate, the peripheral circuit region including a plurality of transistors and a plurality of wirings, and the peripheral circuit region overlapping the stack structure in a direction perpendicular to an upper surface of the substrate.   
     
     
         14 . The semiconductor device of  claim 9 , wherein the second region is above the first region, the third region is above the second region, and
 a first width of the first region is narrower than a second width of the second region, and the second width of the second region is narrower than a third width of the third region, and   a lateral surface of the third region is coplanar with a lateral surface of a lowermost mold insulating layer of the plurality of mold insulating layers, the lowermost mold insulating layer contacting an upper surface of the substrate.   
     
     
         15 . The semiconductor device of  claim 9 , further comprising:
 an impurity region below the recess and having n-type impurities.   
     
     
         16 . The semiconductor device of  claim 9 , further comprising:
 a first upper insulating layer on the stack structure, and   wherein the common source line cuts the first upper insulating layer and the stack structure in a direction parallel to an upper surface of the substrate, and vertically penetrates the first upper insulating layer.   
     
     
         17 . A semiconductor device comprising:
 a substrate including a recess, the substrate defining the recess to include a first region, a second region and a third region having different widths;   a stack structure including a plurality of gate electrodes and a plurality of mold insulating layers alternately stacked on the substrate;   a peripheral circuit region below the substrate and on a base substrate, the peripheral circuit region including a plurality of transistors and a plurality of wirings, the peripheral circuit region overlapping the stack structure in a direction perpendicular to an upper surface of the substrate;   a common source line passing through the stack structure to contact the substrate at the first region of the recess, the common source line extending in a direction parallel to an upper surface of the substrate; and   an insulating spacer between the stack structure and the common source line, the insulating spacer including a silicon compound containing nitrogen.   
     
     
         18 . The semiconductor device of  claim 17 , wherein the insulating spacer includes a combination a silicon compound containing oxygen and the silicon compound containing nitrogen. 
     
     
         19 . The semiconductor device of  claim 17 , wherein the substrate defines a side portion of the recess to include a plurality of stepped portions. 
     
     
         20 . The semiconductor device of  claim 17 , wherein a first space between a lateral surface of a lowermost gate electrode of the plurality of gate electrodes and the common source line is different from a second space between a lateral surface of the substrate at the second region of the recess and the common source line, and
 a lower portion of the insulating spacer includes a bent portion formed according to a shape of the recess, and contacts the substrate at the second region and the third region of the recess.   
     
     
         21 . The semiconductor device of  claim 17 , wherein the second region is above the first region, the third region is above the second region, and
 a first width of the first region is narrower than a second width of the second region, and the second width of the second region is narrower than a third width of the third region, and   a lateral surface of the third region is coplanar with a lateral surface of a lowermost mold insulating layer of the plurality of mold insulating layers, the lowermost mold insulating layer contacting an upper surface of the substrate.