Negative capacitance circuits including temperature-compensation biasings

Abstract

In some examples, an amplifier stage includes a voltage-gain amplifier stage and a negative capacitance circuit coupled to the voltage-gain amplifier stage, the negative capacitance circuit comprising a first transistor that provides a first temperature-biased current.

What is claimed is: 
     
         1 . An amplifier stage, comprising:
 a voltage-gain amplifier stage; and   a negative capacitance circuit coupled to the voltage-gain amplifier stage, the negative capacitance circuit comprising a first transistor that provides a first temperature-biased current.   
     
     
         2 . The amplifier stage of  claim 1 , wherein the voltage-gain amplifier stage further comprises a second transistor that provides a second temperature-biased current. 
     
     
         3 . The amplifier stage of  claim 2 , wherein the second temperature-biased current is directly proportional to a temperature of a die in which the amplifier stage is positioned. 
     
     
         4 . The amplifier stage of  claim 3 , wherein the voltage-gain amplifier stage comprises a first output node and a second output node, wherein the first and the second temperature-biased currents combine to produce substantially constant currents at the first and second output nodes. 
     
     
         5 . The amplifier stage of  claim 1 , wherein the first temperature-biased current is inversely proportional to a temperature of a die in which the amplifier stage is positioned. 
     
     
         6 . The amplifier stage of  claim 1 , wherein a bandwidth of the voltage-gain amplifier stage is less than a bandwidth of the negative capacitance circuit. 
     
     
         7 . The amplifier stage of  claim 1 , wherein the voltage-gain amplifier stage receives a balanced differential signal. 
     
     
         8 . The amplifier stage of  claim 1 , wherein the voltage-gain amplifier stage is coupled to a load capacitor, and wherein the negative capacitance circuit comprises a negative capacitor that is configured to produce an effective capacitance that is less than a load capacitance generated by the load capacitor. 
     
     
         9 . A system comprising:
 a voltage-gain amplifier stage comprising:
 a first transistor comprising a first gate, a first source, and a first drain; 
 a second transistor comprising a second gate, a second source, and a second drain, wherein the first and the second gates are coupled to each other, and wherein the first and second drains are coupled to each other and to a first voltage supply; 
 a third transistor comprising a third gate, a third source, and a third drain; 
 a fourth transistor comprising a fourth gate, a fourth source, and a fourth drain, wherein the third drain is coupled to the first source at a first output node and the fourth drain is coupled to the second source at a second output node; and 
 a fifth transistor having a fifth gate, a fifth source, and a fifth drain, wherein the fifth source is coupled to a ground terminal and the fifth drain is coupled to the third and the fourth sources, wherein the fifth transistor provides a first temperature-biased current; and 
   a negative capacitance circuit comprising:
 a constant current source; 
 a sixth transistor comprising a sixth gate, a sixth source, and a sixth drain; 
 a seventh transistor comprising a seventh gate, a seventh source, and a seventh drain, wherein the seventh drain is coupled to the second output node and the sixth drain is coupled to the first output node; and 
 a negative capacitor coupled to the sixth and seventh sources; 
   wherein the first temperature-biased current is proportional to a temperature of a die in which the voltage-gain amplifier stage is positioned.   
     
     
         10 . A system comprising:
 a voltage-gain amplifier stage comprising:
 a first transistor comprising a first gate, a first source, and a first drain; 
 a second transistor comprising a second gate, a second source, and a second drain, wherein the first and the second gates are coupled to each other, and wherein the first and second drains are coupled to each other and to a first voltage supply; 
 a third transistor comprising a third gate, a third source, and a third drain; 
 a fourth transistor comprising a fourth gate, a fourth source, and a fourth drain, wherein the third drain is coupled to the first source at a first output node and the fourth drain is coupled to the second source at a second output node; and 
 a fifth transistor having a fifth gate, a fifth source, and a fifth drain, wherein the fifth source is coupled to a ground terminal and the fifth drain is coupled to the third and the fourth sources, wherein the fifth transistor provides a first temperature-biased current; and 
   a negative capacitance circuit comprising:
 a constant current source; 
 a sixth transistor comprising a sixth gate, a sixth source, and a sixth drain; 
 a seventh transistor comprising a seventh gate, a seventh source, and a seventh drain, wherein the seventh drain is coupled to the second output node and the sixth drain is coupled to the first output node; and 
 a negative capacitor coupled to the sixth and seventh sources; 
   wherein the second and third temperature-biased currents are inversely proportional to a temperature of a die in which the voltage-gain amplifier stage is positioned.   
     
     
         11 . A system comprising:
 a voltage-gain amplifier stage comprising:
 a first input differential transistor pair; 
 a first output differential transistor pair coupled to the first input differential transistor pair at a first output node and a second output node; and 
 a first transistor that provides a first temperature-biased current, wherein the first transistor couples to the first input differential transistor pair; and 
   a modified negative capacitance circuit comprising:
 a third differential transistor pair; and 
 a second transistor that provides a second temperature-biased current, wherein the second transistor couples to the third differential transistor pair. 
   
     
     
         12 . The system of  claim 11 , wherein the first temperature-biased current is directly proportional to a temperature value, and wherein the second temperature-biased current is inversely proportional to the temperature value. 
     
     
         13 . The system of  claim 11 , wherein the first and the second temperature-biased currents combine to produce a substantially constant current at the first output node and the second output node.