US2019384534A1PendingUtilityA1
Memory system and operating method thereof
Est. expiryJul 19, 2036(~10 yrs left)· nominal 20-yr term from priority
Inventors:Beom-Ju Shin
G06F 3/061G06F 3/0659G06F 13/18G06F 3/0656G06F 13/1673G06F 3/0679G06F 3/0658
59
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Claims
Abstract
A memory system includes a memory device including a plurality of command registers; and a memory controller configured to determine whether an empty command register exists among the plurality of command registers, and transmit a new command to the memory device, when an empty command register exists, wherein, when the new command is transmitted from the memory controller, the memory device stores the transmitted new command in the empty command register.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 . A memory system comprising:
a memory device configured to include a plurality of command registers and a command state register storing execution state information of a plurality of commands stored in the plurality of the command registers; and a memory controller configured to determine whether an empty command register exists among the plurality of command registers based on the execution state information stored in the command state register, and transmit a new command to the memory device, when the empty command register exists.
2 . The memory system according to claim 1 , wherein, when the new command is received from the memory controller, the memory device stores the new command in the empty command register.
3 . The memory system according to claim 1 , wherein the execution state information represents that the command of the respective command registers is execution-pending, currently being executed, or execution-completed.
4 . The memory system according to claim 3 , wherein, when the execution state information of a command stored in at least one of the plurality of the command registers represents the execution-completed, the memory controller determines at least one of the plurality of the command registers is the empty command register.
5 . The memory system according to claim 3 ,
wherein the execution state information of the command stored in the respective command registers is updated according to current execution status of the command, and wherein when the command becomes execution-completed, a corresponding one storing the execution-completed command among the command registers becomes empty.
6 . A method for operating a memory system including a memory device, which includes a plurality of command registers and a command state register storing execution state information of a plurality of commands stored in the plurality of the command registers, and a memory controller, the method comprising:
determining, by the memory controller, whether an empty command register exists among the plurality of command registers based on the execution state information stored in the command state register; and transmitting, by the memory controller, a new command to the memory device when the empty command register exists.
7 . The method of claim 6 , further comprising:
storing, by the memory device, the new command received from the memory controller in the empty command register.
8 . The method of claim 6 , wherein the determining of whether the empty command register exists includes:
checking the execution state information of each of the plurality of the commands stored in the plurality of the command registers; and determining whether at least one of the plurality of the commands is execution-completed.
9 . The method of claim 6 , further comprising:
updating, by the memory device, the execution state information of the command stored in the respective command registers is updated according to current execution status of the command.
10 . The method of claim 6 , wherein the plurality of the commands stored in the plurality of the command registers are executed in order of priority.
11 . A memory system comprising:
a memory device including a plurality of command registers for storing provided commands, and suitable for executing the stored commands; and a memory controller suitable for controlling the memory device by providing the commands to the memory device, wherein a memory controller provides a new command to the memory device when one or more among the stored commands are execution-completed, and wherein the memory device stores the new command in one among the command registers corresponding to the execution-completed commands.
12 . The memory system of claim 11 ,
wherein the memory device further includes a command state register for storing execution statuses of the stored commands, and wherein the memory device updates the execution statuses at least when one or more of the stored commands are execution-completed.
13 . The memory system of claim 12 , wherein the memory controller determine whether to provide the new command according to the execution statuses.
14 . The memory system of claim 13 , wherein the memory device executes the stored command in order of priority.
15 . The memory system of claim 14 , wherein the memory device suspends a command in the process of being executed and having a lower priority, and executes another command having a higher priority, among the stored commands.
16 . A method for operating a memory system including a memory device and a memory controller, the method comprising:
providing, by the memory controller, commands to the memory device; storing, by the memory device, the provided commands in command registers of the memory device; and executing, by the memory device, the stored commands, wherein a new command is provided to the memory device when one or more among the stored commands are execution-completed, and wherein the new command is stored in one among the command registers corresponding to the execution-completed commands.
17 . The method of claim 16 , further comprising:
storing execution statuses of the stored commands; and updating the execution statuses at least when one or more of the stored commands are execution-completed.
18 . The method of claim 17 , wherein the providing of the commands includes determining, by the memory controller, whether to provide the new command according to the execution statuses.
19 . The method of claim 18 , wherein the stored commands are executed in order of priority.
20 . The method of claim 19 , wherein the executing of the stored commands includes:
suspending, by the memory device, a command in the process of being executed and having a lower priority among the stored commands, and executing, by the memory device, another command having a higher priority among the stored commands.Join the waitlist — get patent alerts
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